' ' Defines for ADC.inc ' $ifndef __ADCDEFS_INC $define __ADCDEFS_INC $include pconfig.Inc (* PIC18 A/D conversion peripheral library. The defines and macros are based upon routines included with the Microchip C18 compiler. For 18F devices using version 3.4.0.6 onwards of the Proton+ Compiler *) (* ***** interrupt enable / disable *) $define ADC_INT_ENABLE() PIR1bits_ADIF = 0 : INTCONbits_PEIE = 1 : PIE1bits_ADIE = 1 $define ADC_INT_DISABLE() PIE1bits_ADIE = 0 '----------------------------------------------------------- $if _defined(ADC_V1) Or _defined(ADC_V2) Or _defined(ADC_V3) Or _defined(ADC_V4) Or ' _defined(ADC_V5) Or _defined(ADC_V6) Or _defined(ADC_V8) Or _defined(ADC_V9) Or ' _defined(ADC_V10) Or _defined(ADC_V11) Or _defined(ADC_V12) (* ***** clock source ***** *) $define ADC_FOSC_2 %10001111 ' A/D clock source Fosc/2 $define ADC_FOSC_4 %11001111 ' A/D clock source Fosc/4 $define ADC_FOSC_8 %10011111 ' A/D clock source Fosc/8 $define ADC_FOSC_16 %11011111 ' A/D clock source Fosc/16 $define ADC_FOSC_32 %10101111 ' A/D clock source Fosc/32 $define ADC_FOSC_64 %11101111 ' A/D clock source Fosc/64 $define ADC_FOSC_RC %11111111 ' A/D clock source Internal RC OSC (* ***** acquisition time ***** *) $define ADC_0_TAD %11110001 $define ADC_2_TAD %11110011 $define ADC_4_TAD %11110101 $define ADC_6_TAD %11110111 $define ADC_8_TAD %11111001 $define ADC_12_TAD %11111011 $define ADC_16_TAD %11111101 $define ADC_20_TAD %11111111 $endif '----------------------------------------------------------- $if _defined(ADC_V2) Or _defined(ADC_V3) Or _defined(ADC_V4) Or _defined(ADC_V5) Or ' _defined(ADC_V6) Or _defined(ADC_V8) Or _defined(ADC_V9) Or _defined(ADC_V11) Or _defined(ADC_V12) (* ***** voltage reference ***** *) $define ADC_REF_VDD_VREFMINUS %11111110 ' ADC voltage source VREF+ = VDD and VREF- = ext. source at VREF- $define ADC_REF_VREFPLUS_VREFMINUS %11111111 ' ADC voltage source VREF+ = ext. source at VREF+ and VREF- = ext. source at VREF- $define ADC_REF_VREFPLUS_VSS %11111101 ' ADC voltage source VREF+ = ext. source at VREF+ and VREF- = VSS $define ADC_REF_VDD_VSS %11111100 ' ADC voltage source VREF+ = VDD and VREF- = VSS $endif '-------------------------------------------------------------- (* ***** result justification ***** *) $define ADC_RIGHT_JUST %11111111 ' Right justify A/D result $define ADC_LEFT_JUST %01111111 ' Left justify A/D result '-------------------------------------------------------------- $if _defined(ADC_V1) $define ADC_8ANA_0REF %11110000 ' VREF+=VDD VREF-=VSS all analogue channels (8/0) $define ADC_7ANA_1REF %11110001 ' AN3=VREF+ all analogue channels except AN3 (7/1) $define ADC_5ANA_0REF %11110010 ' VREF+=VDD VREF-=VSS (5/0) $define ADC_4ANA_1REF %11110011 ' AN3=VREF+ (4/1) $define ADC_3ANA_0REF %11110100 ' VREF+=VDD VREF-=VSS (3/0) $define ADC_2ANA_1REF %11110101 ' AN3=VREF+ (2/1) $define ADC_0ANA_0REF %11110111 ' ALL DIGITAL I/O (0/0) $define ADC_6ANA_2REF %11111000 ' AN3=VREF+ AN2=VREF- (6/2) $define ADC_6ANA_0REF %11111001 ' VREF+=VDD VREF-=VSS (6/0) $define ADC_5ANA_1REF %11111010 ' AN3=VREF+ VREF-=VSS (5/1) $define ADC_4ANA_2REF %11111011 ' AN3=VREF+ AN2=VREF- (4/2) $define ADC_3ANA_2REF %11111100 ' AN3=VREF+ AN2=VREF- (3/2) $define ADC_2ANA_2REF %11111101 ' AN3=VREF+ AN2=VREF- (2/2) $define ADC_1ANA_0REF %11111110 ' AN0 is analogue input (1/0) $define ADC_1ANA_2REF %11111111 ' AN3=VREF+ AN2=VREF- AN0=A (1/2) '------------------------------------------------------------------ $elseif _defined(ADC_V2) $define ADC_0ANA %11111111 ' All digital $define ADC_1ANA %11111110 ' analogue: AN0 digital: AN1->15 $define ADC_2ANA %11111101 ' analogue: AN0->1 digital: AN2->15 $define ADC_3ANA %11111100 ' analogue: AN0->2 digital: AN3->15 $define ADC_4ANA %11111011 ' analogue: AN0->3 digital: AN4->15 $define ADC_5ANA %11111010 ' analogue: AN0->4 digital: AN5->15 $define ADC_6ANA %11111001 ' analogue: AN0->5 digital: AN6->15 $define ADC_7ANA %11111000 ' analogue: AN0->6 digital: AN7->15 $define ADC_8ANA %11110111 ' analogue: AN0->7 digital: AN8->15 $define ADC_9ANA %11110110 ' analogue: AN0->8 digital: AN9->15 $define ADC_10ANA %11110101 ' analogue: AN0->9 digital: AN10->15 $define ADC_11ANA %11110100 ' analogue: AN0->10 digital: AN11->15 $define ADC_12ANA %11110011 ' analogue: AN0->11 digital: AN12->15 $define ADC_13ANA %11110010 ' analogue: AN0->12 digital: AN13->15 $define ADC_14ANA %11110001 ' analogue: AN0->13 digital: AN14->15 $define ADC_15ANA %11110000 ' All analogue '---------------------------------------------------------------- $elseif _defined(ADC_V3) $define ADC_0ANA %11111111 ' All digital $define ADC_1ANA %11111110 ' analogue: AN0 $define ADC_2ANA %11111100 ' analogue: AN0,AN1 $define ADC_3ANA %11111000 ' analogue: AN0,AN1,AN2 $define ADC_4ANA %11110000 ' analogue: AN0,AN1,AN2,AN3 $define ADC_5ANA %11100000 ' analogue: AN0,AN1,AN2,AN3,AN4 $define ADC_6ANA %11000000 ' analogue: AN0,AN1,AN2,AN3,AN4,AN5 $define ADC_7ANA %10000000 ' analogue: AN0,AN1,AN2,AN3,AN4,AN5,AN6 '---------------------------------------------------------------- $elseif _defined(ADC_V4) $define ADC_0ANA %00000000 ' All digital $define ADC_1ANA %00000001 ' analogue: AN0 $define ADC_2ANA %00000011 ' analogue: AN0,AN1 $define ADC_3ANA %00000111 ' analogue: AN0,AN1,AN2 $define ADC_4ANA %00001111 ' analogue: AN0,AN1,AN2,AN3 '---------------------------------------------------------------- $elseif _defined(ADC_V5) Or _defined(ADC_V6) Or _defined(ADC_V12) $define ADC_0ANA %00001111 ' All digital $define ADC_1ANA %00001110 ' analogue: AN0 digital: AN1->15 $define ADC_2ANA %00001101 ' analogue: AN0->1 digital: AN2->15 $define ADC_3ANA %00001100 ' analogue: AN0->2 digital: AN3->15 $define ADC_4ANA %00001011 ' analogue: AN0->3 digital: AN4->15 $define ADC_5ANA %00001010 ' analogue: AN0->4 digital: AN5->15 $define ADC_6ANA %00001001 ' analogue: AN0->5 digital: AN6->15 $define ADC_7ANA %00001000 ' analogue: AN0->6 digital: AN7->15 $define ADC_8ANA %00000111 ' analogue: AN0->7 digital: AN8->15 $define ADC_9ANA %00000110 ' analogue: AN0->8 digital: AN9->15 $define ADC_10ANA %00000101 ' analogue: AN0->9 digital: AN10->15 $define ADC_11ANA %00000100 ' analogue: AN0->10 digital: AN11->15 $define ADC_12ANA %00000011 ' analogue: AN0->11 digital: AN12->15 $define ADC_13ANA %00000010 ' analogue: AN0->12 digital: AN13->15 $define ADC_14ANA %00000001 ' analogue: AN0->13 digital: AN14->15 $define ADC_15ANA %00000000 ' All analogue '----------------------------------------------------------------- $elseif _defined(ADC_V8) $define ADC_0ANA %0000000000000000 ' All digital $define ADC_1ANA %0000000000000001 ' analogue: AN0 $define ADC_2ANA %0000000000000011 ' analogue: AN0-AN1 $define ADC_3ANA %0000000000000111 ' analogue: AN0-AN2 $define ADC_4ANA %0000000000001111 ' analogue: AN0-AN3 $define ADC_5ANA %0000000000011111 ' analogue: AN0-AN4 $define ADC_6ANA %0000000000111111 ' analogue: AN0-AN5 $define ADC_7ANA %0000000001111111 ' analogue: AN0-AN6 $define ADC_8ANA %0000000011111111 ' analogue: AN0-AN7 $define ADC_9ANA %0000000111111111 ' analogue: AN0-AN8 $define ADC_10ANA %0000001111111111 ' analogue: AN0-An9 $define ADC_11ANA %0000011111111111 ' analogue: AN0-AN10 $define ADC_12ANA %0000111111111111 ' analogue: AN0-AN11 $define ADC_13ANA %0001111111111111 ' analogue: AN0-AN12 '----------------------------------------------------------------- $elseif _defined(ADC_V9) $define ADC_0ANA %1111111111111111 ' All digital $define ADC_1ANA %1111111111111110 ' analogue: AN0 $define ADC_2ANA %1111111111111100 ' analogue: AN0-AN1 $define ADC_3ANA %1111111111111000 ' analogue: AN0-AN2 $define ADC_4ANA %1111111111110000 ' analogue: AN0-AN3 $define ADC_5ANA %1111111111100000 ' analogue: AN0-AN4 $define ADC_6ANA %1111111111000000 ' analogue: AN0-AN5 $define ADC_7ANA %1111111110000000 ' analogue: AN0-AN6 $define ADC_8ANA %1111111100000000 ' analogue: AN0-AN7 $define ADC_9ANA %1111111000000000 ' analogue: AN0-AN8 $define ADC_10ANA %1111110000000000 ' analogue: AN0-An9 $define ADC_11ANA %1111100000000000 ' analogue: AN0-AN10 $define ADC_12ANA %1111000000000000 ' analogue: AN0-AN11 $define ADC_13ANA %1110000000000000 ' analogue: AN0-AN12 $define ADC_14ANA %1100000000000000 ' analogue: AN0-AN13 $define ADC_15ANA %1000000000000000 ' analogue: AN0-AN14 $define ADC_16ANA %0000000000000000 ' analogue: AN0-AN15 '---------------------------------------------------------------- $elseif _defined(ADC_V11) $define ADC_0ANA %0001111111111111 ' All digital $define ADC_1ANA %0001111111111110 ' analogue: AN0 $define ADC_2ANA %0001111111111100 ' analogue: AN0-AN1 $define ADC_3ANA %0001111111111000 ' analogue: AN0-AN2 $define ADC_4ANA %0001111111110000 ' analogue: AN0-AN3 $define ADC_5ANA %0001111111100000 ' analogue: AN0-AN4 $define ADC_6ANA %0001111111000000 ' analogue: AN0-AN5 $define ADC_7ANA %0001111110000000 ' analogue: AN0-AN6 $define ADC_8ANA %0001111100000000 ' analogue: AN0-AN7 $define ADC_9ANA %0001111000000000 ' analogue: AN0-AN8 $define ADC_10ANA %0001110000000000 ' analogue: AN0-An9 $define ADC_11ANA %0001100000000000 ' analogue: AN0-AN10 $define ADC_12ANA %0001000000000000 ' analogue: AN0-AN11 $define ADC_13ANA %0000000000000000 ' analogue: AN0-AN12 (********Band Gap selection*********) $define ADC_VBG_ON %1000000000000000 'VBG output of Band Gap module is enabled $define ADC_VBG_OFF %0000000000000000 'VBG output of Band Gap module is disabled $define ADC_VBG2_ON %0100000000000000 'VBG/2 output of Band Gap module is enabled $define ADC_VBG2_OFF %0000000000000000 'VBG/2 output of Band Gap module is disabled '---------------------------------------------------------------- $endif $if _defined(ADC_V7) Or _defined(ADC_V7_1) (* ***** A/D conversion type ****** *) $define ADC_CONV_CONTINUOUS %11111111 $define ADC_CONV_SINGLE_SHOT %11110111 (* ***** A/D conversion mode ****** *) $define ADC_MODE_MULTI_CH %11111111 $define ADC_MODE_SINGLE_CH %11111011 (* ***** A/D conversion sequence select ****** *) $define ADC_CONV_SEQ_SEQM1 %11111100 $define ADC_CONV_SEQ_SEQM2 %11111101 $define ADC_CONV_SEQ_STNM1 %11111110 $define ADC_CONV_SEQ_STNM2 %11111111 $define ADC_CONV_SEQ_SCM1 %11111100 $define ADC_CONV_SEQ_SCM2 %11111101 $define ADC_CONV_SEQ_SCM3 %11111110 $define ADC_CONV_SEQ_SCM4 %11111111 (* ***** A/D Vref selection ****** *) $define ADC_REF_VDD_VREFMINUS %10111111 $define ADC_REF_VREFPLUS_VSS %01111111 $define ADC_REF_VREFPLUS_VREFMINUS %11111111 $define ADC_REF_VDD_VSS %00111111 (* ***** A/D FIFO buffer control ****** *) $define ADC_FIFO_EN %11111111 $define ADC_FIFO_DIS %11011111 (* ***** A/D Buffer depth interrupt control ****** *) $define INT_EACH_WR_BUF %00111111 $define INT_2_4_WR_BUF %01111111 $define INT_4_WR_BUF %10111111 (* ***** A/D trigger source ****** *) $define ADC_TRIG_EXT_INT0 %11100001 $define ADC_TRIG_TMR_5 %11100010 $define ADC_TRIG_INP_CAP %11100100 $define ADC_TRIG_CCP2_COM %11101000 $define ADC_TRIG_PCPWM %11110000 (* ***** A/D acquisition time ***** *) $define ADC_0_TAD %10000111 $define ADC_2_TAD %10001111 $define ADC_4_TAD %10010111 $define ADC_6_TAD %10011111 $define ADC_8_TAD %10100111 $define ADC_10_TAD %10101111 $define ADC_12_TAD %10110111 $define ADC_16_TAD %10111111 $define ADC_20_TAD %11000111 $define ADC_24_TAD %11001111 $define ADC_28_TAD %11010111 $define ADC_32_TAD %11011111 $define ADC_36_TAD %11100111 $define ADC_40_TAD %11101111 $define ADC_48_TAD %11110111 $define ADC_64_TAD %11111111 (* ***** A/D clock source ***** *) $define ADC_FOSC_2 %11111000 ' A/D clock source Fosc/2 $define ADC_FOSC_4 %11111100 ' A/D clock source Fosc/4 $define ADC_FRC_4 %11111011 ' A/D clock source FRC/4 $define ADC_FOSC_8 %11111001 ' A/D clock source Fosc/8 $define ADC_FOSC_16 %11111101 ' A/D clock source Fosc/16 $define ADC_FOSC_32 %11111010 ' A/D clock source Fosc/32 $define ADC_FOSC_64 %11111110 ' A/D clock source Fosc/64 $define ADC_FOSC_RC %11111111 ' A/D clock source Internal RC OSC $endif $if _defined(ADC_V11) (* ***** channel selection ***** *) $define ADC_CH0 %10000111 ' Channel 0 $define ADC_CH1 %10001111 ' Channel 1 $define ADC_CH2 %10010111 ' Channel 2 $define ADC_CH3 %10011111 ' Channel 3 $define ADC_CH4 %10100111 ' Channel 4 $define ADC_CH5 %10101111 ' Channel 5 $define ADC_CH6 %10110111 ' Channel 6 $define ADC_CH7 %10111111 ' Channel 7 $define ADC_CH8 %11000111 ' Channel 8 $define ADC_CH9 %11001111 ' Channel 9 $define ADC_CH10 %11010111 ' Channel 10 $define ADC_CH11 %11011111 ' Channel 11 $define ADC_CH12 %11100111 ' Channel 12 $define ADC_CH_CTMU %11101111 ' All analogue inputs are off $define ADC_CH_VDDCORE %11110111 ' VDDCORE Channel $define ADC_CH_VBG %11111111 ' Voltage Band gap channel $else (* ***** channel selection ***** *) $define ADC_CH0 %10000111 ' Channel 0 $define ADC_CH1 %10001111 ' Channel 1 $define ADC_CH2 %10010111 ' Channel 2 $define ADC_CH3 %10011111 ' Channel 3 $define ADC_CH4 %10100111 ' Channel 4 $define ADC_CH5 %10101111 ' Channel 5 $define ADC_CH6 %10110111 ' Channel 6 $define ADC_CH7 %10111111 ' Channel 7 $define ADC_CH8 %11000111 ' Channel 8 $define ADC_CH9 %11001111 ' Channel 9 $define ADC_CH10 %11010111 ' Channel 10 $define ADC_CH11 %11011111 ' Channel 11 $define ADC_CH12 %11100111 ' Channel 12 $define ADC_CH13 %11101111 ' Channel 13 $define ADC_CH14 %11110111 ' Channel 14 $define ADC_CH15 %11111111 ' Channel 15 $endif '----------------------------------------------------------- $if _defined(ADC_V10) (* ***** channel selection ***** *) 'Channels AN0, AN1, AN2, AN12 ------ unused $define ADC_CH3 %10011111 ' Channel 3 $define ADC_CH4 %10100111 ' Channel 4 $define ADC_CH5 %10101111 ' Channel 5 $define ADC_CH6 %10110111 ' Channel 6 $define ADC_CH7 %10111111 ' Channel 7 $define ADC_CH8 %11000111 ' Channel 8 $define ADC_CH9 %11001111 ' Channel 9 $define ADC_CH10 %11010111 ' Channel 10 $define ADC_CH11 %11011111 ' Channel 11 $define TEMP_REF_BANDGAP %11101111 ' Temperature reference from BandGap $define DAC1 %11110111 ' DAC1 $define FVR1 %11111111 ' FVR1 (* ***** Positive Voltage Reference Configuration bits ***** *) $define ADC_REF_VDD_VDD %11111001 ' ADC voltage source VREF+ = AVDD $define ADC_REF_VDD_VREFPLUS %11111011 ' ADC voltage source VREF+ = ext. source at VREF+ $define ADC_REF_VDD_FVREF %11111101 ' ADC voltage source VREF+ = FVREF+ (* ***** Negative Voltage Reference Configuration bits ***** *) $define ADC_REF_VDD_VSS %11111100 ' ADC voltage source VREF- = AVSS $define ADC_REF_VDD_VREFMINUS %11111101 ' ADC voltage source VREF- = ext. source at VREF- $endif '----------------------------------------------------------- $if _defined(ADC_V12) $define ADC_TRIG_CTMU %11111111 'Special trigger from the CTMU $define ADC_TRIG_CCP2 %01111111 'Special trigger from CCP2 $endif '$if _defined(ADC_V4) '$define ADC_SEVT_ENABLE ADCON0bits_SEVTEN = 1 '$define ADC_SEVT_DISABLE ADCON0bits_SEVTEN = 0 '$endif '----------------------------------------------------------- $if _defined(ADC_V6) $define ADC_CALIB() ADCON0bits_ADCAL = 1 $define ADC_NO_CALIB() ADCON0 = ADCON0 & %01111111 $elseif _defined(ADC_V9) $define ADC_CALIB() WDTCONbits_DEVCFG = 0 : ADCON1bits_ADCAL = 1 $define ADC_NO_CALIB() WDTCONbits_DEVCFG = 0 : ADCON1 = ADCON1 & %10111111 $elseif _defined(ADC_V11) $define ADC_CALIB() ADCON1bits_ADCAL = 1 $define ADC_NO_CALIB() ADCON1 = ADCON1 & %10111111 $endif '----------------------------------------------------------- $if _defined(ADC_V7) Or _defined(ADC_V7_1) $define ADC_CH0 0 $define ADC_CH1 1 $define ADC_CH2 2 $define ADC_CH3 3 $define ADC_CH4 4 $define ADC_CH5 5 $define ADC_CH6 6 $define ADC_CH7 7 $define ADC_CH8 8 (* ***** A/D channel from Group A ***** *) $define ADC_CH_GRA_SEL_AN0 0 $define ADC_CH_GRA_SEL_AN4 4 (* ***** A/D channel from Group B ***** *) $define ADC_CH_GRB_SEL_AN1 1 (* ***** A/D channel from Group C ***** *) $define ADC_CH_GRC_SEL_AN2 2 (* ***** A/D channel from Group D ***** *) $define ADC_CH_GRD_SEL_AN3 3 $define ADC_CH_GRA_AN0() ANSEL0 = ANSEL0 | %00000001 : ADCHS = ADCHS | %00000011 : ADCHS = ADCHS & %11111100 $define ADC_CH_GRA_AN4() ANSEL0 = ANSEL0 | %00010000 : ADCHS = ADCHS | %00000011 : ADCHS = ADCHS & %11111101 $define ADC_CH_GRB_AN1() ANSEL0 = ANSEL0 | %00000010 : ADCHS = ADCHS | %00110000 : ADCHS = ADCHS & %11001111 $define ADC_CH_GRC_AN2() ANSEL0 = ANSEL0 | %00000100 : ADCHS = ADCHS | %00001100 : ADCHS = ADCHS & %11110011 $define ADC_CH_GRD_AN3() ANSEL0 = ANSEL0 | %00001000 : ADCHS = ADCHS | %11000000 : ADCHS = ADCHS & %00111111 $endif '----------------------------------------------------------- $if _defined(ADC_V7) $define ADC_CH_GRB_SEL_AN5 5 $define ADC_CH_GRC_SEL_AN6 6 $define ADC_CH_GRD_SEL_AN7 7 $define ADC_CH_GRA_SEL_AN8 8 (* ***** A/D channel from Group B ***** *) $define ADC_CH_GRB_AN5() ANSEL0 = ANSEL0 | %00100000 : ADCHS = ADCHS | %00110000 : ADCHS = ADCHS & %11011111 (* ***** A/D channel from Group C ***** *) $define ADC_CH_GRC_AN6() ANSEL0 = ANSEL0 | %01000000 : ADCHS = ADCHS | %00001100 : ADCHS = ADCHS & %11110111 (* ***** A/D channel from Group D ***** *) $define ADC_CH_GRD_AN7() ANSEL0 = ANSEL0 | %10000000 : ADCHS = ADCHS | %11000000 : ADCHS = ADCHS & %01111111 (* ***** A/D channel from Group A ***** *) $define ADC_CH_GRA_AN8() ANSEL0 = ANSEL0 | %00000001 : ADCHS = ADCHS | %00000011 : ADCHS = ADCHS & %11111110 (* ***** All channel Digital ***** *) $define ALL_CH_DIGITAL() ANSEL0 = 0 : ANSEL1 = 0 (**********************************) $endif $if _defined (ADC_V1) Or _defined (ADC_V2) Or _defined (ADC_V3) Or ' _defined (ADC_V5) Or _defined (ADC_V8) Or _defined (ADC_V4) Or ' _defined (ADC_V6) Or _defined (ADC_V7) Or _defined (ADC_V7_1) Or ' _defined (ADC_V10) Or _defined (ADC_V11) Or _defined (ADC_V12) $define ConvertADC() ADCON0bits_GO_DONE = 1 $elseif _defined (ADC_V9) $define ConvertADC() WDTCONbits_DEVCFG = 0 : ADCON0bits_GO_DONE = 1 $endif $endif