;---------------------------------------------------------- ; Code Produced by the Proton Compiler. Ver 3.5.7.3 ; Copyright Rosetta Technologies/Crownhill Associates Ltd ; Written by Les Johnson. March 2015 ;---------------------------------------------------------- ; #define CONFIG_REQ 1 #define DEBUG@REQ 1 LIST P = 18F2525, F = INHX32, W = 2, X = ON, R = DEC, MM = ON, N = 0, C = 255, T=ON PORTA equ 0X0F80 PORTB equ 0X0F81 PORTC equ 0X0F82 PORTE equ 0X0F84 LATA equ 0X0F89 LATB equ 0X0F8A LATC equ 0X0F8B DDRA equ 0X0F92 TRISA equ 0X0F92 DDRB equ 0X0F93 TRISB equ 0X0F93 DDRC equ 0X0F94 TRISC equ 0X0F94 OSCTUNE equ 0X0F9B PIE1 equ 0X0F9D PIR1 equ 0X0F9E IPR1 equ 0X0F9F PIE2 equ 0X0FA0 PIR2 equ 0X0FA1 IPR2 equ 0X0FA2 EECON1 equ 0X0FA6 EECON2 equ 0X0FA7 EEDATL equ 0X0FA8 EEDATA equ 0X0FA8 EEADR equ 0X0FA9 EEADRH equ 0X0FAA RCSTA equ 0X0FAB TXSTA equ 0X0FAC TXREG equ 0X0FAD RCREG equ 0X0FAE SPBRG equ 0X0FAF SPBRGH equ 0X0FB0 T3CON equ 0X0FB1 TMR3L equ 0X0FB2 TMR3LH equ 0X0FB3 TMR3H equ 0X0FB3 CMCON equ 0X0FB4 CVRCON equ 0X0FB5 BAUDCON equ 0X0FB8 BAUDCTL equ 0X0FB8 CCP2CON equ 0X0FBA CCPR2 equ 0X0FBB CCPR2L equ 0X0FBB CCPR2LH equ 0X0FBC CCPR2H equ 0X0FBC CCP1CON equ 0X0FBD CCPR1 equ 0X0FBE CCPR1L equ 0X0FBE CCPR1LH equ 0X0FBF CCPR1H equ 0X0FBF ADCON2 equ 0X0FC0 ADCON1 equ 0X0FC1 ADCON0 equ 0X0FC2 ADRES equ 0X0FC3 ADRESL equ 0X0FC3 ADRESLH equ 0X0FC4 ADRESH equ 0X0FC4 SSPCON2 equ 0X0FC5 SSPCON1 equ 0X0FC6 SSPSTAT equ 0X0FC7 SSPADD equ 0X0FC8 SSPBUF equ 0X0FC9 T2CON equ 0X0FCA PR2 equ 0X0FCB TMR2 equ 0X0FCC T1CON equ 0X0FCD TMR1L equ 0X0FCE TMR1LH equ 0X0FCF TMR1H equ 0X0FCF RCON equ 0X0FD0 WDTCON equ 0X0FD1 HLVDCON equ 0X0FD2 LVDCON equ 0X0FD2 OSCCON equ 0X0FD3 DEBUG equ 0X0FD4 T0CON equ 0X0FD5 TMR0L equ 0X0FD6 TMR0LH equ 0X0FD7 TMR0H equ 0X0FD7 STATUS equ 0X0FD8 FSR2L equ 0X0FD9 FSR2LH equ 0X0FDA FSR2H equ 0X0FDA PLUSW2 equ 0X0FDB PREINC2 equ 0X0FDC POSTDEC2 equ 0X0FDD POSTINC2 equ 0X0FDE INDF2 equ 0X0FDF BSR equ 0X0FE0 FSR1L equ 0X0FE1 FSR1LH equ 0X0FE2 FSR1H equ 0X0FE2 PLUSW1 equ 0X0FE3 PREINC1 equ 0X0FE4 POSTDEC1 equ 0X0FE5 POSTINC1 equ 0X0FE6 INDF1 equ 0X0FE7 WREG equ 0X0FE8 FSR0L equ 0X0FE9 FSR0LH equ 0X0FEA FSR0H equ 0X0FEA PLUSW0 equ 0X0FEB PREINC0 equ 0X0FEC POSTDEC0 equ 0X0FED POSTINC0 equ 0X0FEE INDF0 equ 0X0FEF INTCON3 equ 0X0FF0 INTCON2 equ 0X0FF1 INTCON equ 0X0FF2 PRODL equ 0X0FF3 PRODLH equ 0X0FF4 PRODH equ 0X0FF4 TABLAT equ 0X0FF5 TBLPTRL equ 0X0FF6 TBLPTRLH equ 0X0FF7 TBLPTRH equ 0X0FF7 TBLPTRU equ 0X0FF8 TBLPTRLHH equ 0X0FF8 PC equ 0X0FF9 PCL equ 0X0FF9 PCLATH equ 0X0FFA PCLATU equ 0X0FFB STKPTR equ 0X0FFC TOS equ 0X0FFD TOSL equ 0X0FFD TOSLH equ 0X0FFE TOSH equ 0X0FFE TOSU equ 0X0FFF _I2C_SCL_PORT=TRISC _I2C_SCL_PIN=3 _I2C_SDA_PORT=TRISC _I2C_SDA_PIN=4 RA0=0 RA1=1 RA2=2 RA3=3 RA4=4 RA5=5 RA6=6 RA7=7 T0CKI=4 AN4=5 SS=5 NOT_SS=5 LVDIN=5 HLVDIN=5 RB0=0 RB1=1 RB2=2 RB3=3 RB4=4 RB5=5 RB6=6 RB7=7 INT0=0 INT1=1 INT2=2 CCP2_PORTB=3 KBI0=4 KBI1=5 KBI2=6 KBI3=7 AN12=0 AN10=1 AN8=2 AN9=3 AN11=4 PGM=5 PGC=6 PGD=7 RC0=0 RC1=1 RC2=2 RC3=3 RC4=4 RC5=5 RC6=6 RC7=7 T1OSO=0 T1OSI=1 CCP1=2 SCK=3 SDI=4 SDO=5 TX=6 RX=7 T13CKI=0 CCP2_PORTC=1 SCL=3 SDA=4 CK=6 T1CKI=0 RE3=3 MCLR=3 NOT_MCLR=3 VPP=3 LATA0=0 LATA1=1 LATA2=2 LATA3=3 LATA4=4 LATA5=5 LATA6=6 LATA7=7 LATB0=0 LATB1=1 LATB2=2 LATB3=3 LATB4=4 LATB5=5 LATB6=6 LATB7=7 LATC0=0 LATC1=1 LATC2=2 LATC3=3 LATC4=4 LATC5=5 LATC6=6 LATC7=7 TRISA0=0 TRISA1=1 TRISA2=2 TRISA3=3 TRISA4=4 TRISA5=5 TRISA6=6 TRISA7=7 TRISB0=0 TRISB1=1 TRISB2=2 TRISB3=3 TRISB4=4 TRISB5=5 TRISB6=6 TRISB7=7 TRISC0=0 TRISC1=1 TRISC2=2 TRISC3=3 TRISC4=4 TRISC5=5 TRISC6=6 TRISC7=7 TUN0=0 TUN1=1 TUN2=2 TUN3=3 TUN4=4 PLLEN=6 INTSRC=7 TMR1IE=0 TMR2IE=1 CCP1IE=2 SSPIE=3 TXIE=4 RCIE=5 ADIE=6 TMR1IF=0 TMR2IF=1 CCP1IF=2 SSPIF=3 TXIF=4 PP_TXIF=4 RCIF=5 PP_RCIF=5 ADIF=6 TMR1IP=0 TMR2IP=1 CCP1IP=2 SSPIP=3 TXIP=4 RCIP=5 ADIP=6 CCP2IE=0 TMR3IE=1 LVDIE=2 BCLIE=3 EEIE=4 CMIE=6 OSCFIE=7 HLVDIE=2 CCP2IF=0 TMR3IF=1 LVDIF=2 BCLIF=3 EEIF=4 CMIF=6 OSCFIF=7 HLVDIF=2 CCP2IP=0 TMR3IP=1 LVDIP=2 BCLIP=3 EEIP=4 CMIP=6 OSCFIP=7 HLVDIP=2 RD=0 PP_RD=0 WR=1 PP_WR=1 WREN=2 PP_WREN=2 WRERR=3 PP_WRERR=3 FREE=4 CFGS=6 EEPGD=7 PP_EEPGD=7 RX9D=0 OERR=1 PP_OERR=1 FERR=2 ADEN=3 CREN=4 PP_CREN=4 SREN=5 RX9=6 SPEN=7 ADDEN=3 TX9D=0 TRMT=1 BRGH=2 SENDB=3 PP_SENDB=3 SYNC=4 TXEN=5 TX9=6 CSRC=7 TMR3ON=0 TMR3CS=1 T3SYNC=2 T3CCP1=3 PP_T3CCP1=3 T3CKPS0=4 T3CKPS1=5 T3CCP2=6 PP_T3CCP2=6 RD16=7 PP_RD16=7 NOT_T3SYNC=2 CM0=0 CM1=1 CM2=2 CIS=3 C1INV=4 C2INV=5 C1OUT=6 C2OUT=7 CVR0=0 CVR1=1 CVR2=2 CVR3=3 CVRSS=4 CVRR=5 CVROE=6 CVREN=7 ABDEN=0 WUE=1 BRG16=3 SCKP=4 RCIDL=6 ABDOVF=7 TXCKP=4 RXDTP=5 RCMT=6 CCP2M0=0 CCP2M1=1 CCP2M2=2 CCP2M3=3 CCP2Y=4 CCP2X=5 DC2B0=4 DC2B1=5 CCP1M0=0 CCP1M1=1 CCP1M2=2 CCP1M3=3 CCP1Y=4 CCP1X=5 DC1B0=4 DC1B1=5 ADCS0=0 ADCS1=1 ADCS2=2 ACQT0=3 ACQT1=4 ACQT2=5 ADFM=7 PCFG0=0 PCFG1=1 PCFG2=2 PCFG3=3 VCFG0=4 VCFG1=5 ADON=0 PP_ADON=0 GO=1 CHS0=2 CHS1=3 CHS2=4 CHS3=5 DONE=1 NOT_DONE=1 GO_DONE=1 PP_GO_DONE=1 SEN=0 PP_SEN=0 RSEN=1 PP_RSEN=1 PEN=2 PP_PEN=2 RCEN=3 PP_RCEN=3 ACKEN=4 PP_ACKEN=4 ACKDT=5 PP_ACKDT=5 ACKSTAT=6 GCEN=7 SSPM0=0 SSPM1=1 SSPM2=2 SSPM3=3 CKP=4 SSPEN=5 SSPOV=6 WCOL=7 BF=0 UA=1 CKE=6 SMP=7 NOT_W=2 NOT_A=5 R_W=2 PP_R_W=2 D_A=5 NOT_WRITE=2 NOT_ADDRESS=5 T2CKPS0=0 PP_T2CKPS0=0 T2CKPS1=1 PP_T2CKPS1=1 TMR2ON=2 PP_TMR2ON=2 T2OUTPS0=3 T2OUTPS1=4 T2OUTPS2=5 T2OUTPS3=6 TOUTPS0=3 TOUTPS1=4 TOUTPS2=5 TOUTPS3=6 TMR1ON=0 TMR1CS=1 T1SYNC=2 T1OSCEN=3 T1CKPS0=4 T1CKPS1=5 T1RUN=6 NOT_T1SYNC=2 BOR=0 POR=1 PD=2 TO=3 RI=4 SBOREN=6 IPEN=7 NOT_BOR=0 NOT_POR=1 NOT_PD=2 NOT_TO=3 NOT_RI=4 SWDTEN=0 SWDTE=0 LVDL0=0 LVDL1=1 LVDL2=2 LVDL3=3 LVDEN=4 IRVST=5 LVV0=0 LVV1=1 LVV2=2 LVV3=3 BGST=5 HLVDL0=0 HLVDL1=1 HLVDL2=2 HLVDL3=3 HLVDEN=4 VDIRMAG=7 IVRST=5 SCS0=0 SCS1=1 IOFS=2 OSTS=3 IRCF0=4 IRCF1=5 IRCF2=6 IDLEN=7 FLTS=2 T0PS0=0 T0PS1=1 T0PS2=2 PSA=3 T0SE=4 T0CS=5 T016BIT=6 TMR0ON=7 T08BIT=6 C=0 DC=1 Z=2 OV=3 N=4 INT1F=0 INT2F=1 INT1E=3 INT2E=4 INT1P=6 INT2P=7 INT1IF=0 INT2IF=1 INT1IE=3 INT2IE=4 INT1IP=6 INT2IP=7 RBIP=0 TMR0IP=2 INTEDG2=4 INTEDG1=5 INTEDG0=6 RBPU=7 NOT_RBPU=7 RBIF=0 INT0F=1 TMR0IF=2 RBIE=3 INT0E=4 TMR0IE=5 PEIE=6 GIE=7 INT0IF=1 T0IF=2 INT0IE=4 T0IE=5 GIEL=6 GIEH=7 STKPTR0=0 STKPTR1=1 STKPTR2=2 STKPTR3=3 STKPTR4=4 STKUNF=6 STKOVF=7 SP0=0 SP1=1 SP2=2 SP3=3 SP4=4 STKFUL=7 __MAXRAM 0X0FFF __BADRAM 0X0F83 __BADRAM 0X0F85-0X0F88 __BADRAM 0X0F8C-0X0F91 __BADRAM 0X0F95-0X0F9A __BADRAM 0X0F9C __BADRAM 0X0FA3-0X0FA5 __BADRAM 0X0FB6-0X0FB7 __BADRAM 0X0FB9 config1h equ 0X300001 config2l equ 0X300002 config2h equ 0X300003 config3h equ 0X300005 config4l equ 0X300006 config5l equ 0X300008 config5h equ 0X300009 config6l equ 0X30000A config6h equ 0X30000B config7l equ 0X30000C config7h equ 0X30000D OSC_LP_1 equ 0XF0 OSC_XT_1 equ 0XF1 OSC_HS_1 equ 0XF2 OSC_RC_1 equ 0XF3 OSC_EC_1 equ 0XF4 OSC_ECIO6_1 equ 0XF5 OSC_HSPLL_1 equ 0XF6 OSC_RCIO6_1 equ 0XF7 OSC_INTIO67_1 equ 0XF8 OSC_INTIO7_1 equ 0XF9 FCMEN_OFF_1 equ 0XBF FCMEN_ON_1 equ 0XFF IESO_OFF_1 equ 0X7F IESO_ON_1 equ 0XFF PWRT_ON_2 equ 0XFE PWRT_OFF_2 equ 0XFF BOREN_OFF_2 equ 0XF9 BOREN_ON_2 equ 0XFB BOREN_NOSLP_2 equ 0XFD BOREN_SBORDIS_2 equ 0XFF BORV_0_2 equ 0XE7 BORV_1_2 equ 0XEF BORV_2_2 equ 0XF7 BORV_3_2 equ 0XFF WDT_OFF_2 equ 0XFE WDT_ON_2 equ 0XFF WDTPS_1_2 equ 0XE1 WDTPS_2_2 equ 0XE3 WDTPS_4_2 equ 0XE5 WDTPS_8_2 equ 0XE7 WDTPS_16_2 equ 0XE9 WDTPS_32_2 equ 0XEB WDTPS_64_2 equ 0XED WDTPS_128_2 equ 0XEF WDTPS_256_2 equ 0XF1 WDTPS_512_2 equ 0XF3 WDTPS_1024_2 equ 0XF5 WDTPS_2048_2 equ 0XF7 WDTPS_4096_2 equ 0XF9 WDTPS_8192_2 equ 0XFB WDTPS_16384_2 equ 0XFD WDTPS_32768_2 equ 0XFF MCLRE_OFF_3 equ 0X7F MCLRE_ON_3 equ 0XFF LPT1OSC_OFF_3 equ 0XFB LPT1OSC_ON_3 equ 0XFF PBADEN_OFF_3 equ 0XFD PBADEN_ON_3 equ 0XFF CCP2MX_PORTBE_3 equ 0XFE CCP2MX_PORTC_3 equ 0XFF STVREN_OFF_4 equ 0XFE STVREN_ON_4 equ 0XFF LVP_OFF_4 equ 0XFB LVP_ON_4 equ 0XFF XINST_OFF_4 equ 0XBF XINST_ON_4 equ 0XFF DEBUG_ON_4 equ 0X7F DEBUG_OFF_4 equ 0XFF CP0_ON_5 equ 0XFE CP0_OFF_5 equ 0XFF CP1_ON_5 equ 0XFD CP1_OFF_5 equ 0XFF CP2_ON_5 equ 0XFB CP2_OFF_5 equ 0XFF CPB_ON_5 equ 0XBF CPB_OFF_5 equ 0XFF CPD_ON_5 equ 0X7F CPD_OFF_5 equ 0XFF WRT0_ON_6 equ 0XFE WRT0_OFF_6 equ 0XFF WRT1_ON_6 equ 0XFD WRT1_OFF_6 equ 0XFF WRT2_ON_6 equ 0XFB WRT2_OFF_6 equ 0XFF WRTB_ON_6 equ 0XBF WRTB_OFF_6 equ 0XFF WRTC_ON_6 equ 0XDF WRTC_OFF_6 equ 0XFF WRTD_ON_6 equ 0X7F WRTD_OFF_6 equ 0XFF EBTR0_ON_7 equ 0XFE EBTR0_OFF_7 equ 0XFF EBTR1_ON_7 equ 0XFD EBTR1_OFF_7 equ 0XFF EBTR2_ON_7 equ 0XFB EBTR2_OFF_7 equ 0XFF EBTRB_ON_7 equ 0XBF EBTRB_OFF_7 equ 0XFF DEVID1 equ 0X3FFFFE DEVID2 equ 0X3FFFFF IDLOC0 equ 0X200000 __IDLOC0 equ 0X200000 IDLOC1 equ 0X200001 __IDLOC1 equ 0X200001 IDLOC2 equ 0X200002 __IDLOC2 equ 0X200002 IDLOC3 equ 0X200003 __IDLOC3 equ 0X200003 IDLOC4 equ 0X200004 __IDLOC4 equ 0X200004 IDLOC5 equ 0X200005 __IDLOC5 equ 0X200005 IDLOC6 equ 0X200006 __IDLOC6 equ 0X200006 IDLOC7 equ 0X200007 __IDLOC7 equ 0X200007 #define __18F2525 1 #define XTAL 40 #define _CORE 16 #define _MAXRAM 3955 #define _RAM_END 3967 #define _MAXMEM 0XC000 #define _ADC 10 #define _ADC_RES 10 #define _EEPROM 1024 #define RAM_BANKS 15 #define _USART 1 #define _USB 0 #define _USB#RAM_START 0 #define _FLASH 1 #define _CWRITE_BLOCK 64 #define BANK0_START 128 #define BANK0_END 255 #define BANK1_START 256 #define BANK1_END 511 #define BANK2_START 512 #define BANK2_END 767 #define BANK3_START 768 #define BANK3_END 1023 #define BANK4_START 1024 #define BANK4_END 1279 #define BANK5_START 1280 #define BANK5_END 1535 #define BANK6_START 1536 #define BANK6_END 1791 #define BANK7_START 1792 #define BANK7_END 2047 #define BANK8_START 2048 #define BANK8_END 2303 #define BANK9_START 2304 #define BANK9_END 2559 #define BANK10_START 2560 #define BANK10_END 2815 #define BANK11_START 2816 #define BANK11_END 3071 #define BANK12_START 3072 #define BANK12_END 3327 #define BANK13_START 3328 #define BANK13_END 3583 #define BANK14_START 3584 #define BANK14_END 3839 #define BANKA_START 0 #define BANKA_END 127 #define _SYSTEM_VARIABLE_COUNT 61 #define LCD#TYPE 0 #define __INTERRUPTS_ENABLED 1 #define __HIGH_INTERRUPTS_ENABLED 1 #define __LOW_INTERRUPTS_ENABLED 1 #define clrw clrf WREG #define negw negf WREG #define skpc btfss STATUS,0 #define skpnc btfsc STATUS,0 #define clrc bcf STATUS,0 #define setc bsf STATUS,0 #define skpz btfss STATUS,2 #define skpnz btfsc STATUS,2 #define clrz bcf STATUS,2 #define setz bsf STATUS,2 #define INIT_USART_INTERRUPT#REQ 1 #define CLEAR_SERIAL_BUFFER#REQ 1 GEN = 0 PBP#VAR0 = 1 PBP#VAR0H = 2 PBP#VAR0HH = 3 PBP#VAR0HHH = 4 PP0 = 5 PP0H = 6 PP1 = 7 PP1H = 8 PP2 = 9 PP2H = 10 PP3 = 11 PP3H = 12 PP4 = 13 PP4H = 14 PP5 = 15 PP6H = 16 Bytein = 17 _I = 18 statusbyte = 19 noteUit = 20 release = 21 noteAan = 22 velo = 23 notePres = 24 pres = 25 Ctrl = 26 value = 27 prog = 28 veltim0 = 29 veltim0H = 30 veltim0HH = 31 veltim0HHH = 32 veltim1 = 33 veltim1H = 34 veltim1HH = 35 veltim1HHH = 36 Velflags = 37 VelflagsH = 38 notes = 39 notesH = 40 Rate0 = 41 Rate0H = 42 velo0 = 43 velo0H = 44 Pres0 = 45 time = 46 timeH = 47 timeHH = 48 timeHHH = 49 _T = 50 tog = 51 Nxt = 52 NxtH = 53 NxtHH = 54 NxtHHH = 55 idx = 56 USART_FSR1_Save = 57 USART_FSR1_SaveH = 58 IndexIn = 59 IndexOut = 60 TimVals = 61 TimValsH = 62 TimValsHH = 63 TimValsHHH = 64 variable TimVals#0=61,TimVals#0H=62,TimVals#0HH=63,TimVals#0HHH=64 variable TimVals#1=65,TimVals#1H=66,TimVals#1HH=67,TimVals#1HHH=68 Ringbuffer = 69 variable Ringbuffer#0=69,Ringbuffer#1=70,Ringbuffer#2=71,Ringbuffer#3=72 variable Ringbuffer#4=73,Ringbuffer#5=74,Ringbuffer#6=75,Ringbuffer#7=76 variable Ringbuffer#8=77,Ringbuffer#9=78,Ringbuffer#10=79,Ringbuffer#11=80 variable Ringbuffer#12=81,Ringbuffer#13=82,Ringbuffer#14=83,Ringbuffer#15=84 variable Ringbuffer#16=85,Ringbuffer#17=86,Ringbuffer#18=87,Ringbuffer#19=88 variable Ringbuffer#20=89,Ringbuffer#21=90,Ringbuffer#22=91,Ringbuffer#23=92 variable Ringbuffer#24=93,Ringbuffer#25=94,Ringbuffer#26=95,Ringbuffer#27=96 variable Ringbuffer#28=97,Ringbuffer#29=98,Ringbuffer#30=99,Ringbuffer#31=100 variable Ringbuffer#32=101,Ringbuffer#33=102,Ringbuffer#34=103,Ringbuffer#35=104 variable Ringbuffer#36=105,Ringbuffer#37=106,Ringbuffer#38=107,Ringbuffer#39=108 variable Ringbuffer#40=109,Ringbuffer#41=110,Ringbuffer#42=111,Ringbuffer#43=112 variable Ringbuffer#44=113,Ringbuffer#45=114,Ringbuffer#46=115,Ringbuffer#47=116 variable Ringbuffer#48=117,Ringbuffer#49=118,Ringbuffer#50=119,Ringbuffer#51=120 variable Ringbuffer#52=121,Ringbuffer#53=122,Ringbuffer#54=123,Ringbuffer#55=124 variable Ringbuffer#56=125,Ringbuffer#57=126,Ringbuffer#58=127,Ringbuffer#59=128 variable Ringbuffer#60=129,Ringbuffer#61=130,Ringbuffer#62=131,Ringbuffer#63=132 variable Ringbuffer#64=133,Ringbuffer#65=134,Ringbuffer#66=135,Ringbuffer#67=136 variable Ringbuffer#68=137,Ringbuffer#69=138,Ringbuffer#70=139,Ringbuffer#71=140 variable Ringbuffer#72=141,Ringbuffer#73=142,Ringbuffer#74=143,Ringbuffer#75=144 variable Ringbuffer#76=145,Ringbuffer#77=146,Ringbuffer#78=147,Ringbuffer#79=148 variable Ringbuffer#80=149,Ringbuffer#81=150,Ringbuffer#82=151,Ringbuffer#83=152 variable Ringbuffer#84=153,Ringbuffer#85=154,Ringbuffer#86=155,Ringbuffer#87=156 variable Ringbuffer#88=157,Ringbuffer#89=158,Ringbuffer#90=159,Ringbuffer#91=160 variable Ringbuffer#92=161,Ringbuffer#93=162,Ringbuffer#94=163,Ringbuffer#95=164 variable Ringbuffer#96=165,Ringbuffer#97=166,Ringbuffer#98=167,Ringbuffer#99=168 variable Ringbuffer#100=169,Ringbuffer#101=170,Ringbuffer#102=171,Ringbuffer#103=172 variable Ringbuffer#104=173,Ringbuffer#105=174,Ringbuffer#106=175,Ringbuffer#107=176 variable Ringbuffer#108=177,Ringbuffer#109=178,Ringbuffer#110=179,Ringbuffer#111=180 variable Ringbuffer#112=181,Ringbuffer#113=182,Ringbuffer#114=183,Ringbuffer#115=184 variable Ringbuffer#116=185,Ringbuffer#117=186,Ringbuffer#118=187,Ringbuffer#119=188 variable Ringbuffer#120=189,Ringbuffer#121=190,Ringbuffer#122=191,Ringbuffer#123=192 variable Ringbuffer#124=193,Ringbuffer#125=194,Ringbuffer#126=195,Ringbuffer#127=196 variable Ringbuffer#128=197,Ringbuffer#129=198,Ringbuffer#130=199,Ringbuffer#131=200 variable Ringbuffer#132=201,Ringbuffer#133=202,Ringbuffer#134=203,Ringbuffer#135=204 variable Ringbuffer#136=205,Ringbuffer#137=206,Ringbuffer#138=207,Ringbuffer#139=208 variable Ringbuffer#140=209,Ringbuffer#141=210,Ringbuffer#142=211,Ringbuffer#143=212 variable Ringbuffer#144=213,Ringbuffer#145=214,Ringbuffer#146=215,Ringbuffer#147=216 variable Ringbuffer#148=217,Ringbuffer#149=218,Ringbuffer#150=219,Ringbuffer#151=220 variable Ringbuffer#152=221,Ringbuffer#153=222,Ringbuffer#154=223,Ringbuffer#155=224 variable Ringbuffer#156=225,Ringbuffer#157=226,Ringbuffer#158=227,Ringbuffer#159=228 variable Ringbuffer#160=229,Ringbuffer#161=230,Ringbuffer#162=231,Ringbuffer#163=232 variable Ringbuffer#164=233,Ringbuffer#165=234,Ringbuffer#166=235,Ringbuffer#167=236 variable Ringbuffer#168=237,Ringbuffer#169=238,Ringbuffer#170=239,Ringbuffer#171=240 variable Ringbuffer#172=241,Ringbuffer#173=242,Ringbuffer#174=243,Ringbuffer#175=244 variable Ringbuffer#176=245,Ringbuffer#177=246,Ringbuffer#178=247,Ringbuffer#179=248 variable Ringbuffer#180=249,Ringbuffer#181=250,Ringbuffer#182=251,Ringbuffer#183=252 variable Ringbuffer#184=253,Ringbuffer#185=254,Ringbuffer#186=255,Ringbuffer#187=256 variable Ringbuffer#188=257,Ringbuffer#189=258,Ringbuffer#190=259,Ringbuffer#191=260 variable Ringbuffer#192=261,Ringbuffer#193=262,Ringbuffer#194=263,Ringbuffer#195=264 variable Ringbuffer#196=265,Ringbuffer#197=266,Ringbuffer#198=267,Ringbuffer#199=268 variable Ringbuffer#200=269,Ringbuffer#201=270,Ringbuffer#202=271,Ringbuffer#203=272 variable Ringbuffer#204=273,Ringbuffer#205=274,Ringbuffer#206=275,Ringbuffer#207=276 variable Ringbuffer#208=277,Ringbuffer#209=278,Ringbuffer#210=279,Ringbuffer#211=280 variable Ringbuffer#212=281,Ringbuffer#213=282,Ringbuffer#214=283,Ringbuffer#215=284 variable Ringbuffer#216=285,Ringbuffer#217=286,Ringbuffer#218=287,Ringbuffer#219=288 variable Ringbuffer#220=289,Ringbuffer#221=290,Ringbuffer#222=291,Ringbuffer#223=292 variable Ringbuffer#224=293,Ringbuffer#225=294,Ringbuffer#226=295,Ringbuffer#227=296 variable Ringbuffer#228=297,Ringbuffer#229=298,Ringbuffer#230=299,Ringbuffer#231=300 variable Ringbuffer#232=301,Ringbuffer#233=302,Ringbuffer#234=303,Ringbuffer#235=304 variable Ringbuffer#236=305,Ringbuffer#237=306,Ringbuffer#238=307,Ringbuffer#239=308 variable Ringbuffer#240=309,Ringbuffer#241=310,Ringbuffer#242=311,Ringbuffer#243=312 variable Ringbuffer#244=313,Ringbuffer#245=314,Ringbuffer#246=315,Ringbuffer#247=316 variable Ringbuffer#248=317,Ringbuffer#249=318,Ringbuffer#250=319,Ringbuffer#251=320 variable Ringbuffer#252=321,Ringbuffer#253=322,Ringbuffer#254=323,Ringbuffer#255=324 Dur = 325 DurH = 326 variable Dur#0=325,Dur#0H=326,Dur#1=327,Dur#1H=328 variable Dur#2=329,Dur#2H=330,Dur#3=331,Dur#3H=332 variable Dur#4=333,Dur#4H=334,Dur#5=335,Dur#5H=336 variable Dur#6=337,Dur#6H=338,Dur#7=339,Dur#7H=340 variable Dur#8=341,Dur#8H=342,Dur#9=343,Dur#9H=344 variable Dur#10=345,Dur#10H=346,Dur#11=347,Dur#11H=348 variable Dur#12=349,Dur#12H=350,Dur#13=351,Dur#13H=352 variable Dur#14=353,Dur#14H=354,Dur#15=355,Dur#15H=356 variable Dur#16=357,Dur#16H=358,Dur#17=359,Dur#17H=360 variable Dur#18=361,Dur#18H=362,Dur#19=363,Dur#19H=364 variable Dur#20=365,Dur#20H=366,Dur#21=367,Dur#21H=368 variable Dur#22=369,Dur#22H=370,Dur#23=371,Dur#23H=372 variable Dur#24=373,Dur#24H=374,Dur#25=375,Dur#25H=376 variable Dur#26=377,Dur#26H=378,Dur#27=379,Dur#27H=380 variable Dur#28=381,Dur#28H=382,Dur#29=383,Dur#29H=384 variable Dur#30=385,Dur#30H=386,Dur#31=387,Dur#31H=388 variable Dur#32=389,Dur#32H=390,Dur#33=391,Dur#33H=392 variable Dur#34=393,Dur#34H=394,Dur#35=395,Dur#35H=396 variable Dur#36=397,Dur#36H=398,Dur#37=399,Dur#37H=400 variable Dur#38=401,Dur#38H=402,Dur#39=403,Dur#39H=404 variable Dur#40=405,Dur#40H=406,Dur#41=407,Dur#41H=408 variable Dur#42=409,Dur#42H=410,Dur#43=411,Dur#43H=412 variable Dur#44=413,Dur#44H=414,Dur#45=415,Dur#45H=416 variable Dur#46=417,Dur#46H=418,Dur#47=419,Dur#47H=420 variable Dur#48=421,Dur#48H=422,Dur#49=423,Dur#49H=424 variable Dur#50=425,Dur#50H=426,Dur#51=427,Dur#51H=428 variable Dur#52=429,Dur#52H=430,Dur#53=431,Dur#53H=432 variable Dur#54=433,Dur#54H=434,Dur#55=435,Dur#55H=436 variable Dur#56=437,Dur#56H=438,Dur#57=439,Dur#57H=440 variable Dur#58=441,Dur#58H=442,Dur#59=443,Dur#59H=444 variable Dur#60=445,Dur#60H=446,Dur#61=447,Dur#61H=448 variable Dur#62=449,Dur#62H=450,Dur#63=451,Dur#63H=452 variable Dur#64=453,Dur#64H=454,Dur#65=455,Dur#65H=456 variable Dur#66=457,Dur#66H=458,Dur#67=459,Dur#67H=460 variable Dur#68=461,Dur#68H=462,Dur#69=463,Dur#69H=464 variable Dur#70=465,Dur#70H=466,Dur#71=467,Dur#71H=468 variable Dur#72=469,Dur#72H=470,Dur#73=471,Dur#73H=472 variable Dur#74=473,Dur#74H=474,Dur#75=475,Dur#75H=476 variable Dur#76=477,Dur#76H=478,Dur#77=479,Dur#77H=480 variable Dur#78=481,Dur#78H=482,Dur#79=483,Dur#79H=484 variable Dur#80=485,Dur#80H=486,Dur#81=487,Dur#81H=488 variable Dur#82=489,Dur#82H=490,Dur#83=491,Dur#83H=492 variable Dur#84=493,Dur#84H=494,Dur#85=495,Dur#85H=496 variable Dur#86=497,Dur#86H=498,Dur#87=499,Dur#87H=500 variable Dur#88=501,Dur#88H=502,Dur#89=503,Dur#89H=504 variable Dur#90=505,Dur#90H=506,Dur#91=507,Dur#91H=508 variable Dur#92=509,Dur#92H=510,Dur#93=511,Dur#93H=512 variable Dur#94=513,Dur#94H=514,Dur#95=515,Dur#95H=516 variable Dur#96=517,Dur#96H=518,Dur#97=519,Dur#97H=520 variable Dur#98=521,Dur#98H=522,Dur#99=523,Dur#99H=524 variable Dur#100=525,Dur#100H=526,Dur#101=527,Dur#101H=528 variable Dur#102=529,Dur#102H=530,Dur#103=531,Dur#103H=532 variable Dur#104=533,Dur#104H=534,Dur#105=535,Dur#105H=536 variable Dur#106=537,Dur#106H=538,Dur#107=539,Dur#107H=540 variable Dur#108=541,Dur#108H=542,Dur#109=543,Dur#109H=544 variable Dur#110=545,Dur#110H=546,Dur#111=547,Dur#111H=548 variable Dur#112=549,Dur#112H=550,Dur#113=551,Dur#113H=552 variable Dur#114=553,Dur#114H=554,Dur#115=555,Dur#115H=556 variable Dur#116=557,Dur#116H=558,Dur#117=559,Dur#117H=560 variable Dur#118=561,Dur#118H=562,Dur#119=563,Dur#119H=564 variable Dur#120=565,Dur#120H=566,Dur#121=567,Dur#121H=568 variable Dur#122=569,Dur#122H=570,Dur#123=571,Dur#123H=572 variable Dur#124=573,Dur#124H=574,Dur#125=575,Dur#125H=576 variable Dur#126=577,Dur#126H=578,Dur#127=579,Dur#127H=580 _Low__Context_Store = 581 variable _Low__Context_Store#0=581,_Low__Context_Store#1=582,_Low__Context_Store#2=583 #define StBit Bytein,7 #define maxtim timeHHH,7 #define tg tog,0 #define FSR0SaveInt PP0 #define FSR0SaveIntH PP0H #define USART_FSR0_Save FSR0SaveInt #define USART_FSR0_SaveH FSR0SaveIntH #define USART_FSR0 FSR0L #define USART_FSR0H FSR0LH #define USART_FSR1 FSR1L #define USART_FSR1H FSR1LH #define __OPTIMISER_LEVEL 3 #define __XTAL 40 #define PWMminF 2442 #define PWMminFH 9 #define fPWM 32767 #define fPWMH 127 #define lite0 122 #define U_Hold 184 #define U_Velo 255 #define Midichannel 0 #define NoteOff_Status 128 #define NoteOn_Status 144 #define Keypres_Status 160 #define Control_Status 176 #define ProgChange_Status 192 #define Aftertouch_Status 208 #define Pitchbend_Status 224 #define __HSERIAL_BAUD 31250 #define __HSERIAL_TXSTA 36 HSERIAL_SPBRG = 79 HSERIAL_TXSTA = 36 HSERIAL_RCSTA = 144 HSERIAL_BAUD = 31250 proton#code#start org 0X000000 nop nop goto proton#main#start org 0X000008 bra High_Prior_Interrupt org 0X000018 bra Low_Prior_Interrupt HRSIN#REQ = 1 HRSINX#REQ = 1 HRSIN#CLROERR = 1 __HPWM_ movwf 14,0 movlw 150 movwf 5,0 movlw 152 movwf 6,0 rcall __DIVIDE_U1616_ btfsc 4056,2,0 bcf 4042,PP_T2CKPS0,0 btfss 4056,2,0 bsf 4042,PP_T2CKPS0,0 addlw 252 btfss 4056,0,0 bcf 4042,PP_T2CKPS1,0 btfsc 4056,0,0 bsf 4042,PP_T2CKPS1,0 movlw 128 movwf 5,0 movlw 150 movwf 6,0 movlw 152 movwf 9,0 clrf 10,0 btfsc 4042,PP_T2CKPS0,0 rcall HPW@2S btfsc 4042,PP_T2CKPS1,0 rcall HPW@2S rcall __DIVIDE_INT_U1616_ decf 5,W,0 movwf 4043,0 movff 5,7 movff 6,8 movf 0,W,0 movwf 11,0 movwf 12,0 incfsz 0,W,0 clrf 12,0 rcall __MULTIPLY_U1616_ movf 10,W,0 decfsz 14,F,0 bra HPW@SK1 movwf 4030,0 movlw 12 movwf 4029,0 btfsc 9,7,0 bsf 4029,5,0 btfsc 9,6,0 bsf 4029,4,0 bcf TRISB,2,0 HPWM@FIN bsf 4042,PP_TMR2ON,0 return HPW@SK1 movwf 4027,0 movlw 12 movwf 4026,0 btfsc 9,7,0 bsf 4026,5,0 btfsc 9,6,0 bsf 4026,4,0 bcf TRISC,1,0 bra HPWM@FIN HPW@2S rcall HPW@2L HPW@2L bcf 4056,0,0 rrcf 9,F,0 rrcf 6,F,0 rrcf 5,F,0 return __DELAY_MS_ clrf 8,0 __DELAY_MS_W_ movwf 7,0 DLY@P movlw 255 addwf 7,F,0 addwfc 8,F,0 bra $ + 2 btfss 4056,0,0 return movlw 3 movwf 6,0 movlw 230 rcall __DELAY_US_W_ bra DLY@P __DELAY_US_ clrf 6,0 __DELAY_US_W_ addlw 254 movwf 5,0 clrf 4072,0 subwfb 6,F,0 btfss 4056,0,0 return nop decf 5,F,0 bra $ + 2 bra $ - 14 __DIVIDE_U1616_ clrf 10,0 clrf 9,0 __DIVIDE_INT_U1616_ movlw 16 movwf 4083,0 DV@LP rlcf 6,W,0 rlcf 9,F,0 rlcf 10,F,0 movf 7,W,0 subwf 9,W,0 movf 8,W,0 subwfb 10,W,0 bnc D@K movf 7,W,0 subwf 9,F,0 movf 8,W,0 subwfb 10,F,0 bsf 4056,0,0 D@K rlcf 5,F,0 rlcf 6,F,0 decfsz 4083,F,0 bra DV@LP movf 5,W,0 return __MULTIPLY_U1616_ movf 7,W,0 mulwf 11,0 movff 4083,9 movff 4084,10 movf 8,W,0 mulwf 11,0 movf 4083,W,0 addwf 10,F,0 movf 7,W,0 mulwf 12,0 movf 4083,W,0 addwf 10,F,0 movf 9,W,0 return proton#main#start movlw 79 movwf SPBRG,0 movlw 36 movwf TXSTA,0 movlw 144 movwf RCSTA,0 movlb 0 F1_SOF equ $ ; PP2-POWER.BAS F2_SOF equ $ ; 18F2525.INC F2_EOF equ $ ; 18F2525.INC F1_000042 equ $ ; IN [PP2-POWER.BAS] DECLARE ALL_DIGITAL = TRUE movlw 15 movwf ADCON1,0 movlw 7 movwf CMCON,0 F1_000044 equ $ ; IN [PP2-POWER.BAS] CLEAR SSPCON1.5 bcf SSPCON1,5,0 F1_000045 equ $ ; IN [PP2-POWER.BAS] TRISA = %01000011 movlw 67 movwf TRISA,0 F1_000046 equ $ ; IN [PP2-POWER.BAS] TRISB = %11100000 movlw 224 movwf TRISB,0 F1_000047 equ $ ; IN [PP2-POWER.BAS] TRISC = %11000000 movlw 192 movwf TRISC,0 F3_SOF equ $ ; PP2_IRQ_POW.INC F3_000066 equ $ ; IN [PP2_IRQ_POW.INC] GOTO _OVER_IRQ_HANDLER bra _Over_IRQ_Handler High_Prior_Interrupt _Timer0_IRQ F3_000078 equ $ ; IN [PP2_IRQ_POW.INC] IF INTCON.2 = 1 THEN btfss INTCON,2,0 bra _LBL__3 F3_000079 equ $ ; IN [PP2_IRQ_POW.INC] CLEAR INTCON.2 bcf INTCON,2,0 F3_000084 equ $ ; IN [PP2_IRQ_POW.INC] BTG PORTB.5 btg PORTB,5 F3_000085 equ $ ; IN [PP2_IRQ_POW.INC] RETFIE FAST retfie 1 F3_000086 equ $ ; IN [PP2_IRQ_POW.INC] ENDIF _LBL__3 _UART_IRQ F3_000088 equ $ ; IN [PP2_IRQ_POW.INC] IF PIR1.5 = 1 THEN btfss PIR1,5,0 bra _LBL__5 F3_000089 equ $ ; IN [PP2_IRQ_POW.INC] MOVLW 6 movlw 6 F3_000090 equ $ ; IN [PP2_IRQ_POW.INC] ANDWF RCSTA,W andwf RCSTA,W F3_000091 equ $ ; IN [PP2_IRQ_POW.INC] BNZ _UART_ERROR bnz _Uart_Error F3_000092 equ $ ; IN [PP2_IRQ_POW.INC] USART_FSR1_SAVE = USART_FSR1 movff FSR1LH,USART_FSR1_SaveH movff FSR1L,USART_FSR1_Save F3_000093 equ $ ; IN [PP2_IRQ_POW.INC] INC INDEXIN incf IndexIn,F,0 F3_000103 equ $ ; IN [PP2_IRQ_POW.INC] USART_FSR1 = VARPTR RINGBUFFER lfsr 1,69 F3_000104 equ $ ; IN [PP2_IRQ_POW.INC] USART_FSR1 = USART_FSR1 + INDEXIN movf IndexIn,W,0 addwf FSR1L,F,0 movlw 0 addwfc FSR1LH,F,0 F3_000105 equ $ ; IN [PP2_IRQ_POW.INC] INDF1 = RCREG movff RCREG,INDF1 F3_000106 equ $ ; IN [PP2_IRQ_POW.INC] USART_FSR1 = USART_FSR1_SAVE movff USART_FSR1_SaveH,FSR1LH movff USART_FSR1_Save,FSR1L F3_000108 equ $ ; IN [PP2_IRQ_POW.INC] RETFIE FAST retfie 1 _Uart_Error F3_000110 equ $ ; IN [PP2_IRQ_POW.INC] WREG = RCREG movf RCREG,W,0 F3_000111 equ $ ; IN [PP2_IRQ_POW.INC] WREG = RCREG movf RCREG,W,0 F3_000112 equ $ ; IN [PP2_IRQ_POW.INC] CLEAR RCSTA.4 bcf RCSTA,4,0 F3_000113 equ $ ; IN [PP2_IRQ_POW.INC] SET RCSTA.4 bsf RCSTA,4,0 F3_000114 equ $ ; IN [PP2_IRQ_POW.INC] ENDIF _LBL__5 F3_000115 equ $ ; IN [PP2_IRQ_POW.INC] RETFIE FAST retfie 1 HRSIN: F3_000120 equ $ ; IN [PP2_IRQ_POW.INC] IF INDEXIN <> INDEXOUT THEN movf IndexIn,W,0 subwf IndexOut,W,0 bz _LBL__7 F3_000121 equ $ ; IN [PP2_IRQ_POW.INC] INC INDEXOUT incf IndexOut,F,0 F3_000122 equ $ ; IN [PP2_IRQ_POW.INC] USART_FSR0_SAVE = USART_FSR0 movff FSR0LH,FSR0SaveIntH movff FSR0L,FSR0SaveInt F3_000123 equ $ ; IN [PP2_IRQ_POW.INC] USART_FSR0 = VARPTR RINGBUFFER lfsr 0,69 F3_000124 equ $ ; IN [PP2_IRQ_POW.INC] USART_FSR0 = USART_FSR0 + INDEXOUT movf IndexOut,W,0 addwf FSR0L,F,0 movlw 0 addwfc FSR0LH,F,0 F3_000125 equ $ ; IN [PP2_IRQ_POW.INC] WREG = INDF0 movf INDF0,W,0 F3_000126 equ $ ; IN [PP2_IRQ_POW.INC] PP0 = WREG movwf PP0,0 F3_000127 equ $ ; IN [PP2_IRQ_POW.INC] USART_FSR0 = USART_FSR0_SAVE movff FSR0SaveIntH,FSR0LH movff FSR0SaveInt,FSR0L F3_000128 equ $ ; IN [PP2_IRQ_POW.INC] SET STATUS.0 bsf STATUS,0,0 F3_000129 equ $ ; IN [PP2_IRQ_POW.INC] RET return 0 bra _LBL__8 _LBL__7 F3_000130 equ $ ; IN [PP2_IRQ_POW.INC] ELSE F3_000131 equ $ ; IN [PP2_IRQ_POW.INC] WREG = 255 setf WREG,0 F3_000132 equ $ ; IN [PP2_IRQ_POW.INC] PP0 = WREG movwf PP0,0 F3_000133 equ $ ; IN [PP2_IRQ_POW.INC] BTFSS STATUS,C btfss STATUS,C F3_000134 equ $ ; IN [PP2_IRQ_POW.INC] RET return 0 F3_000135 equ $ ; IN [PP2_IRQ_POW.INC] ENDIF _LBL__8 F3_000136 equ $ ; IN [PP2_IRQ_POW.INC] RET return 0 _Init_Usart F3_000152 equ $ ; IN [PP2_IRQ_POW.INC] CLEAR INDEXIN clrf IndexIn,0 F3_000153 equ $ ; IN [PP2_IRQ_POW.INC] CLEAR INDEXOUT clrf IndexOut,0 F3_000154 equ $ ; IN [PP2_IRQ_POW.INC] SET PIE1.5 bsf PIE1,5,0 F3_000156 equ $ ; IN [PP2_IRQ_POW.INC] SET IPR1.5 bsf IPR1,5,0 F3_000158 equ $ ; IN [PP2_IRQ_POW.INC] SET INTCON.7 bsf INTCON,7,0 F3_000159 equ $ ; IN [PP2_IRQ_POW.INC] SET INTCON.6 bsf INTCON,6,0 F3_000161 equ $ ; IN [PP2_IRQ_POW.INC] RETURN return 0 _Clear_Usart_Buffer F3_000176 equ $ ; IN [PP2_IRQ_POW.INC] PIE1.5 = 0 bcf PIE1,5,0 F3_000177 equ $ ; IN [PP2_IRQ_POW.INC] CLEAR RINGBUFFER lfsr 0,Ringbuffer movlw 1 movwf PRODLH,0 clrf PRODL,0 _PBLB__9 decf PRODL,F,0 movlw 0 subwfb PRODLH,F,0 clrf POSTINC0,0 movf PRODH,W,0 iorwf PRODL,W,0 bnz _PBLB__9 F3_000178 equ $ ; IN [PP2_IRQ_POW.INC] CLEAR INDEXIN clrf IndexIn,0 F3_000179 equ $ ; IN [PP2_IRQ_POW.INC] CLEAR INDEXOUT clrf IndexOut,0 F3_000180 equ $ ; IN [PP2_IRQ_POW.INC] SET PIE1.5 bsf PIE1,5,0 F3_000181 equ $ ; IN [PP2_IRQ_POW.INC] RETURN return 0 Low_Prior_Interrupt Timer3_ISR F3_000189 equ $ ; IN [PP2_IRQ_POW.INC] CONTEXT SAVE bcf INTCON,7,0 movff BSR,_Low__Context_Store#0 movff STATUS,_Low__Context_Store#1 movff WREG,_Low__Context_Store#2 bsf INTCON,7,0 movlb 0 F3_000190 equ $ ; IN [PP2_IRQ_POW.INC] CLEAR PIR2.1 bcf PIR2,1,0 F3_000196 equ $ ; IN [PP2_IRQ_POW.INC] CONTEXT RESTORE bcf INTCON,7,0 movff _Low__Context_Store#0,BSR movff _Low__Context_Store#1,STATUS movff _Low__Context_Store#2,WREG bsf INTCON,7,0 retfie HRSOUT F3_000208 equ $ ; IN [PP2_IRQ_POW.INC] BTFSS PIR1.4 btfss PIR1,4 F3_000209 equ $ ; IN [PP2_IRQ_POW.INC] BRA ($ - 2) bra ($ - 2) F3_000210 equ $ ; IN [PP2_IRQ_POW.INC] MOVWF TXREG movwf TXREG F3_000211 equ $ ; IN [PP2_IRQ_POW.INC] RETURN return 0 _Over_IRQ_Handler F3_EOF equ $ ; PP2_IRQ_POW.INC MAIN F1_000139 equ $ ; IN [PP2-POWER.BAS] HIGH PORTB.5 bcf TRISB,5,0 bsf LATB,5,0 F1_000140 equ $ ; IN [PP2-POWER.BAS] DELAYMS 10 movlw 10 rcall __DELAY_MS_ F1_000141 equ $ ; IN [PP2-POWER.BAS] LOW PORTB.5 bcf TRISB,5,0 bcf LATB,5,0 F1_000142 equ $ ; IN [PP2-POWER.BAS] LOW PORTA.4 bcf TRISA,4,0 bcf LATA,4,0 F1_000143 equ $ ; IN [PP2-POWER.BAS] LOW PORTA.5 bcf TRISA,5,0 bcf LATA,5,0 F1_000144 equ $ ; IN [PP2-POWER.BAS] LOW PORTA.3 bcf TRISA,3,0 bcf LATA,3,0 F1_000145 equ $ ; IN [PP2-POWER.BAS] LOW PORTC.5 bcf TRISC,5,0 bcf LATC,5,0 F1_000146 equ $ ; IN [PP2-POWER.BAS] LOW PORTB.2 bcf TRISB,2,0 bcf LATB,2,0 F1_000147 equ $ ; IN [PP2-POWER.BAS] HPWM 2, 0, FPWM clrf GEN,0 movlw 127 movwf PP1H,0 setf PP1,0 movlw 2 rcall __HPWM_ F1_000148 equ $ ; IN [PP2-POWER.BAS] HPWM 1, 0, FPWM clrf GEN,0 movlw 127 movwf PP1H,0 setf PP1,0 movlw 1 rcall __HPWM_ F1_000149 equ $ ; IN [PP2-POWER.BAS] CLEAR NOTES clrf notesH,0 clrf notes,0 F1_000150 equ $ ; IN [PP2-POWER.BAS] CLEAR VELFLAGS clrf VelflagsH,0 clrf Velflags,0 F1_000151 equ $ ; IN [PP2-POWER.BAS] SET TIMVALS lfsr 0,TimVals movlw 8 setf POSTINC0,0 decfsz WREG,F,0 bra $ - 4 F1_000152 equ $ ; IN [PP2-POWER.BAS] CLEAR PRES0 clrf Pres0,0 F1_000153 equ $ ; IN [PP2-POWER.BAS] CLEAR RATE0 clrf Rate0H,0 clrf Rate0,0 F1_000154 equ $ ; IN [PP2-POWER.BAS] CLEAR VELO0 clrf velo0H,0 clrf velo0,0 F1_000156 equ $ ; IN [PP2-POWER.BAS] INIT_USART_INTERRUPT variable max_params=10,INIT_USART_INTERRUPT_RETURN=0,prm_count=0 rcall _Init_Usart F1_000158 equ $ ; IN [PP2-POWER.BAS] CLEAR_SERIAL_BUFFER variable max_params=10,CLEAR_SERIAL_BUFFER_RETURN=0,prm_count=0 rcall _Clear_Usart_Buffer F1_000170 equ $ ; IN [PP2-POWER.BAS] CLEAR T1CON clrf T1CON,0 F1_000171 equ $ ; IN [PP2-POWER.BAS] CLEAR INTCON.2 bcf INTCON,2,0 F1_000172 equ $ ; IN [PP2-POWER.BAS] SET INTCON.5 bsf INTCON,5,0 F1_000173 equ $ ; IN [PP2-POWER.BAS] T0CON = %10000111 movlw 135 movwf T0CON,0 F1_000207 equ $ ; IN [PP2-POWER.BAS] CLEAR T3CON clrf T3CON,0 F1_000208 equ $ ; IN [PP2-POWER.BAS] CLEAR PIR2.1 bcf PIR2,1,0 F1_000209 equ $ ; IN [PP2-POWER.BAS] SET PIE2.1 bsf PIE2,1,0 F1_000212 equ $ ; IN [PP2-POWER.BAS] SET RCON.7 bsf RCON,7,0 F1_000213 equ $ ; IN [PP2-POWER.BAS] CLEAR IPR2.1 bcf IPR2,1,0 F1_000215 equ $ ; IN [PP2-POWER.BAS] T3CON = %10110001 movlw 177 movwf T3CON,0 F1_000224 equ $ ; IN [PP2-POWER.BAS] IPR1.0 = 0 bcf IPR1,0,0 F1_000225 equ $ ; IN [PP2-POWER.BAS] INTCON.6 = 1 bsf INTCON,6,0 F1_000226 equ $ ; IN [PP2-POWER.BAS] INTCON.7 = 1 bsf INTCON,7,0 F1_000237 equ $ ; IN [PP2-POWER.BAS] GOSUB DUR_LOOKUP rcall Dur_Lookup LOOP F1_000241 equ $ ; IN [PP2-POWER.BAS] INC T incf _T,F,0 F1_000242 equ $ ; IN [PP2-POWER.BAS] IF T.1 = TG THEN clrf WREG,0 btfsc _T,1,0 addlw 1 btfsc tog,0,0 sublw 1 bnz _LBL__11 F1_000243 equ $ ; IN [PP2-POWER.BAS] BTG TG btg tog,0 F1_000244 equ $ ; IN [PP2-POWER.BAS] INC TIME incf time,F,0 movlw 0 addwfc timeH,F,0 addwfc timeHH,F,0 addwfc timeHHH,F,0 F1_000245 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__11 F1_000247 equ $ ; IN [PP2-POWER.BAS] BYTEIN = HRSIN rcall HRSIN movwf Bytein,0 Midi_Parse F1_000250 equ $ ; IN [PP2-POWER.BAS] IF BYTEIN > CONTROL_STATUS THEN movlw 177 subwf Bytein,W,0 bnc _LBL__13 F1_000251 equ $ ; IN [PP2-POWER.BAS] IF BYTEIN > 253 THEN movlw 254 subwf Bytein,W,0 bc _LBL__16 _LBL__15 F1_000255 equ $ ; IN [PP2-POWER.BAS] ELSE F1_000256 equ $ ; IN [PP2-POWER.BAS] CLEAR STATUSBYTE clrf statusbyte,0 F1_000257 equ $ ; IN [PP2-POWER.BAS] END IF _LBL__16 F1_000258 equ $ ; IN [PP2-POWER.BAS] GOTO CHECK_TIMERS bra Check_Timers F1_000259 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__13 F1_000260 equ $ ; IN [PP2-POWER.BAS] IF STBIT =1 THEN btfss Bytein,7,0 bra _LBL__18 F1_000262 equ $ ; IN [PP2-POWER.BAS] CLEAR STATUSBYTE clrf statusbyte,0 F1_000263 equ $ ; IN [PP2-POWER.BAS] SELECT BYTEIN F1_000264 equ $ ; IN [PP2-POWER.BAS] CASE NOTEOFF_STATUS movlw 128 subwf Bytein,W,0 bnz _LBL__20 F1_000265 equ $ ; IN [PP2-POWER.BAS] STATUSBYTE = BYTEIN movff Bytein,statusbyte F1_000266 equ $ ; IN [PP2-POWER.BAS] SET NOTEUIT setf noteUit,0 F1_000267 equ $ ; IN [PP2-POWER.BAS] SET RELEASE setf release,0 bra _LBL__19 _LBL__20 F1_000268 equ $ ; IN [PP2-POWER.BAS] CASE NOTEON_STATUS movlw 144 subwf Bytein,W,0 bnz _LBL__23 F1_000269 equ $ ; IN [PP2-POWER.BAS] STATUSBYTE = BYTEIN movff Bytein,statusbyte F1_000270 equ $ ; IN [PP2-POWER.BAS] SET NOTEAAN setf noteAan,0 F1_000271 equ $ ; IN [PP2-POWER.BAS] SET VELO setf velo,0 bra _LBL__19 _LBL__23 F1_000272 equ $ ; IN [PP2-POWER.BAS] CASE KEYPRES_STATUS movlw 160 subwf Bytein,W,0 bnz _LBL__25 F1_000273 equ $ ; IN [PP2-POWER.BAS] STATUSBYTE = BYTEIN movff Bytein,statusbyte F1_000274 equ $ ; IN [PP2-POWER.BAS] NOTEPRES = 255 setf notePres,0 F1_000275 equ $ ; IN [PP2-POWER.BAS] PRES = 255 setf pres,0 bra _LBL__19 _LBL__25 F1_000276 equ $ ; IN [PP2-POWER.BAS] CASE CONTROL_STATUS movlw 176 subwf Bytein,W,0 bnz _LBL__27 F1_000277 equ $ ; IN [PP2-POWER.BAS] STATUSBYTE = BYTEIN movff Bytein,statusbyte F1_000278 equ $ ; IN [PP2-POWER.BAS] SET CTRL setf Ctrl,0 F1_000279 equ $ ; IN [PP2-POWER.BAS] SET VALUE setf value,0 F1_000290 equ $ ; IN [PP2-POWER.BAS] END SELECT _LBL__27 _LBL__19 bra _LBL__28 _LBL__18 F1_000291 equ $ ; IN [PP2-POWER.BAS] ELSE F1_000292 equ $ ; IN [PP2-POWER.BAS] SELECT STATUSBYTE F1_000293 equ $ ; IN [PP2-POWER.BAS] CASE 0 movf statusbyte,F,0 bnz _LBL__30 F1_000294 equ $ ; IN [PP2-POWER.BAS] GOTO CHECK_TIMERS bra Check_Timers bra _LBL__29 _LBL__30 F1_000295 equ $ ; IN [PP2-POWER.BAS] CASE NOTEOFF_STATUS movlw 128 subwf statusbyte,W,0 bnz _LBL__33 F1_000296 equ $ ; IN [PP2-POWER.BAS] IF NOTEUIT = 255 THEN incf noteUit,W,0 bnz _LBL__35 F1_000297 equ $ ; IN [PP2-POWER.BAS] NOTEUIT = BYTEIN movff Bytein,noteUit bra _LBL__36 _LBL__35 F1_000298 equ $ ; IN [PP2-POWER.BAS] ELSE F1_000299 equ $ ; IN [PP2-POWER.BAS] RELEASE = BYTEIN movff Bytein,release F1_000300 equ $ ; IN [PP2-POWER.BAS] SELECT NOTEUIT F1_000301 equ $ ; IN [PP2-POWER.BAS] CASE LITE0 movlw 122 subwf noteUit,W,0 bnz _LBL__38 F1_000302 equ $ ; IN [PP2-POWER.BAS] LOW PORTA.3 bcf TRISA,3,0 bcf LATA,3,0 F1_000303 equ $ ; IN [PP2-POWER.BAS] CLEAR VELFLAGS.0 bcf Velflags,0,0 F1_000304 equ $ ; IN [PP2-POWER.BAS] CLEAR NOTES.0 bcf notes,0,0 F1_000305 equ $ ; IN [PP2-POWER.BAS] SET TIMVALS[0] setf TimVals#0HHH,0 setf TimVals#0HH,0 setf TimVals#0H,0 setf TimVals#0,0 F1_000306 equ $ ; IN [PP2-POWER.BAS] CASE ELSE bra _LBL__41 _LBL__38 F1_000307 equ $ ; IN [PP2-POWER.BAS] SET NOTEUIT setf noteUit,0 F1_000308 equ $ ; IN [PP2-POWER.BAS] GOTO CHECK_TIMERS bra Check_Timers F1_000309 equ $ ; IN [PP2-POWER.BAS] END SELECT _LBL__41 _LBL__37 F1_000310 equ $ ; IN [PP2-POWER.BAS] SET NOTEUIT setf noteUit,0 F1_000311 equ $ ; IN [PP2-POWER.BAS] GOTO RESORT bra resort F1_000312 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__36 bra _LBL__29 _LBL__33 F1_000314 equ $ ; IN [PP2-POWER.BAS] CASE NOTEON_STATUS movlw 144 subwf statusbyte,W,0 btfss STATUS,2,0 bra _LBL__43 F1_000315 equ $ ; IN [PP2-POWER.BAS] IF NOTEAAN = 255 THEN incf noteAan,W,0 bnz _LBL__45 F1_000316 equ $ ; IN [PP2-POWER.BAS] NOTEAAN = BYTEIN movff Bytein,noteAan bra _LBL__46 _LBL__45 F1_000317 equ $ ; IN [PP2-POWER.BAS] ELSE F1_000318 equ $ ; IN [PP2-POWER.BAS] VELO = BYTEIN movff Bytein,velo F1_000319 equ $ ; IN [PP2-POWER.BAS] IF VELO = 0 THEN movf velo,F,0 bnz _LBL__48 F1_000320 equ $ ; IN [PP2-POWER.BAS] SELECT NOTEAAN F1_000321 equ $ ; IN [PP2-POWER.BAS] CASE LITE0 movlw 122 subwf noteAan,W,0 bnz _LBL__50 F1_000322 equ $ ; IN [PP2-POWER.BAS] LOW PORTA.3 bcf TRISA,3,0 bcf LATA,3,0 F1_000323 equ $ ; IN [PP2-POWER.BAS] CLEAR VELFLAGS.0 bcf Velflags,0,0 F1_000324 equ $ ; IN [PP2-POWER.BAS] CLEAR NOTES.0 bcf notes,0,0 F1_000325 equ $ ; IN [PP2-POWER.BAS] SET TIMVALS[0] setf TimVals#0HHH,0 setf TimVals#0HH,0 setf TimVals#0H,0 setf TimVals#0,0 F1_000326 equ $ ; IN [PP2-POWER.BAS] CASE ELSE bra _LBL__53 _LBL__50 F1_000327 equ $ ; IN [PP2-POWER.BAS] SET NOTEAAN setf noteAan,0 F1_000328 equ $ ; IN [PP2-POWER.BAS] GOTO CHECK_TIMERS bra Check_Timers F1_000329 equ $ ; IN [PP2-POWER.BAS] END SELECT _LBL__53 _LBL__49 F1_000330 equ $ ; IN [PP2-POWER.BAS] SET NOTEAAN setf noteAan,0 F1_000331 equ $ ; IN [PP2-POWER.BAS] GOTO RESORT bra resort bra _LBL__54 _LBL__48 F1_000332 equ $ ; IN [PP2-POWER.BAS] ELSE F1_000333 equ $ ; IN [PP2-POWER.BAS] SELECT NOTEAAN F1_000334 equ $ ; IN [PP2-POWER.BAS] CASE LITE0 movlw 122 subwf noteAan,W,0 bnz _LBL__56 F1_000335 equ $ ; IN [PP2-POWER.BAS] HIGH PORTA.3 bcf TRISA,3,0 bsf LATA,3,0 F1_000336 equ $ ; IN [PP2-POWER.BAS] IF VELO < 127 THEN movlw 127 subwf velo,W,0 bc _LBL__59 F1_000337 equ $ ; IN [PP2-POWER.BAS] SET VELFLAGS.0 bsf Velflags,0,0 F1_000338 equ $ ; IN [PP2-POWER.BAS] RATE0 = DUR[VELO] lfsr 0,Dur bcf STATUS,0,0 rlcf velo,W,0 addwf FSR0L,F,0 movlw 0 addwfc FSR0H,F,0 movff POSTINC0,Rate0 movff INDF0,Rate0H F1_000339 equ $ ; IN [PP2-POWER.BAS] TIMVALS[0] = TIME + RATE0 movf Rate0,W,0 addwf time,W,0 movwf PBP#VAR0,0 movf Rate0H,W,0 addwfc timeH,W,0 movwf PBP#VAR0H,0 movlw 0 addwfc timeHH,W,0 movwf PBP#VAR0HH,0 movlw 0 addwfc timeHHH,W,0 movwf PBP#VAR0HHH,0 movff PBP#VAR0HHH,TimVals#0HHH movff PBP#VAR0HH,TimVals#0HH movff PBP#VAR0H,TimVals#0H movff PBP#VAR0,TimVals#0 F1_000340 equ $ ; IN [PP2-POWER.BAS] SET NOTES.0 bsf notes,0,0 bra _LBL__60 _LBL__59 F1_000341 equ $ ; IN [PP2-POWER.BAS] ELSE F1_000342 equ $ ; IN [PP2-POWER.BAS] CLEAR VELFLAGS.0 bcf Velflags,0,0 F1_000343 equ $ ; IN [PP2-POWER.BAS] CLEAR NOTES.0 bcf notes,0,0 F1_000344 equ $ ; IN [PP2-POWER.BAS] SET TIMVALS[0] setf TimVals#0HHH,0 setf TimVals#0HH,0 setf TimVals#0H,0 setf TimVals#0,0 F1_000345 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__60 F1_000346 equ $ ; IN [PP2-POWER.BAS] CASE ELSE bra _LBL__62 _LBL__56 F1_000347 equ $ ; IN [PP2-POWER.BAS] SET NOTEAAN setf noteAan,0 F1_000348 equ $ ; IN [PP2-POWER.BAS] GOTO CHECK_TIMERS bra Check_Timers F1_000349 equ $ ; IN [PP2-POWER.BAS] END SELECT _LBL__62 _LBL__55 F1_000350 equ $ ; IN [PP2-POWER.BAS] SET NOTEAAN setf noteAan,0 F1_000351 equ $ ; IN [PP2-POWER.BAS] GOTO RESORT bra resort F1_000352 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__54 F1_000353 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__46 F1_000354 equ $ ; IN [PP2-POWER.BAS] GOTO CHECK_TIMERS bra Check_Timers bra _LBL__29 _LBL__43 F1_000355 equ $ ; IN [PP2-POWER.BAS] CASE KEYPRES_STATUS movlw 160 subwf statusbyte,W,0 bnz _LBL__64 F1_000356 equ $ ; IN [PP2-POWER.BAS] IF NOTEPRES = 255 THEN incf notePres,W,0 bnz _LBL__66 F1_000357 equ $ ; IN [PP2-POWER.BAS] NOTEPRES = BYTEIN movff Bytein,notePres bra _LBL__67 _LBL__66 F1_000358 equ $ ; IN [PP2-POWER.BAS] ELSE F1_000359 equ $ ; IN [PP2-POWER.BAS] PRES = BYTEIN movff Bytein,pres F1_000360 equ $ ; IN [PP2-POWER.BAS] GOSUB KEYPRES rcall KeyPres F1_000361 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__67 F1_000362 equ $ ; IN [PP2-POWER.BAS] GOTO CHECK_TIMERS bra Check_Timers bra _LBL__29 _LBL__64 F1_000363 equ $ ; IN [PP2-POWER.BAS] CASE CONTROL_STATUS movlw 176 subwf statusbyte,W,0 bnz _LBL__69 F1_000364 equ $ ; IN [PP2-POWER.BAS] IF CTRL = 255 THEN incf Ctrl,W,0 bnz _LBL__71 F1_000365 equ $ ; IN [PP2-POWER.BAS] CTRL = BYTEIN movff Bytein,Ctrl bra _LBL__72 _LBL__71 F1_000366 equ $ ; IN [PP2-POWER.BAS] ELSE F1_000367 equ $ ; IN [PP2-POWER.BAS] VALUE = BYTEIN movff Bytein,value F1_000368 equ $ ; IN [PP2-POWER.BAS] GOSUB CONTROLLER rcall Controller F1_000369 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__72 F1_000370 equ $ ; IN [PP2-POWER.BAS] GOTO CHECK_TIMERS bra Check_Timers F1_000371 equ $ ; IN [PP2-POWER.BAS] CASE ELSE bra _LBL__74 _LBL__69 F1_000372 equ $ ; IN [PP2-POWER.BAS] GOTO CHECK_TIMERS bra Check_Timers F1_000373 equ $ ; IN [PP2-POWER.BAS] END SELECT _LBL__74 _LBL__29 F1_000374 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__28 resort F1_000377 equ $ ; IN [PP2-POWER.BAS] GOSUB SORTTIMERS rcall SortTimers Check_Timers F1_000380 equ $ ; IN [PP2-POWER.BAS] IF IDX < 2 THEN movlw 2 subwf idx,W,0 btfsc STATUS,0,0 bra _LBL__76 F1_000381 equ $ ; IN [PP2-POWER.BAS] IF TIME >= NXT THEN movf Nxt,W,0 subwf time,W,0 movf NxtH,W,0 subwfb timeH,W,0 movf NxtHH,W,0 subwfb timeHH,W,0 movf NxtHHH,W,0 subwfb timeHHH,W,0 bnc _LBL__78 F1_000383 equ $ ; IN [PP2-POWER.BAS] SET NXT.31 bsf NxtHHH,7,0 F1_000385 equ $ ; IN [PP2-POWER.BAS] SELECT IDX F1_000386 equ $ ; IN [PP2-POWER.BAS] CASE 0 movf idx,F,0 bnz _LBL__80 F1_000387 equ $ ; IN [PP2-POWER.BAS] IF NOTES.0 = 0 THEN btfsc notes,0,0 bra _LBL__83 F1_000389 equ $ ; IN [PP2-POWER.BAS] CLEAR VELFLAGS.0 bcf Velflags,0,0 F1_000390 equ $ ; IN [PP2-POWER.BAS] SET TIMVALS[0] setf TimVals#0HHH,0 setf TimVals#0HH,0 setf TimVals#0H,0 setf TimVals#0,0 F1_000391 equ $ ; IN [PP2-POWER.BAS] CLEAR PORTA.3 bcf LATA,3,0 bra _LBL__84 _LBL__83 F1_000392 equ $ ; IN [PP2-POWER.BAS] ELSE F1_000394 equ $ ; IN [PP2-POWER.BAS] IF VELFLAGS.0 = 1 THEN btfss Velflags,0,0 bra _LBL__86 F1_000395 equ $ ; IN [PP2-POWER.BAS] BTG PORTA.3 btg PORTA,3 F1_000396 equ $ ; IN [PP2-POWER.BAS] TIMVALS[0] = TIME + RATE0 movf Rate0,W,0 addwf time,W,0 movwf PBP#VAR0,0 movf Rate0H,W,0 addwfc timeH,W,0 movwf PBP#VAR0H,0 movlw 0 addwfc timeHH,W,0 movwf PBP#VAR0HH,0 movlw 0 addwfc timeHHH,W,0 movwf PBP#VAR0HHH,0 movff PBP#VAR0HHH,TimVals#0HHH movff PBP#VAR0HH,TimVals#0HH movff PBP#VAR0H,TimVals#0H movff PBP#VAR0,TimVals#0 F1_000397 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__86 F1_000398 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__84 bra _LBL__79 _LBL__80 F1_000399 equ $ ; IN [PP2-POWER.BAS] CASE 1 movlw 1 subwf idx,W,0 bnz _LBL__88 F1_000400 equ $ ; IN [PP2-POWER.BAS] CLEAR VELFLAGS.1 bcf Velflags,1,0 F1_000401 equ $ ; IN [PP2-POWER.BAS] SET TIMVALS[1] setf TimVals#1HHH,0 setf TimVals#1HH,0 setf TimVals#1H,0 setf TimVals#1,0 F1_000405 equ $ ; IN [PP2-POWER.BAS] END SELECT _LBL__88 _LBL__79 F1_000406 equ $ ; IN [PP2-POWER.BAS] GOSUB SORTTIMERS rcall SortTimers F1_000408 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__78 F1_000410 equ $ ; IN [PP2-POWER.BAS] IF MAXTIM = 1 THEN btfss timeHHH,7,0 bra _LBL__90 F1_000411 equ $ ; IN [PP2-POWER.BAS] CLEAR TIME clrf timeHHH,0 clrf timeHH,0 clrf timeH,0 clrf time,0 F1_000412 equ $ ; IN [PP2-POWER.BAS] CLEAR VELFLAGS clrf VelflagsH,0 clrf Velflags,0 F1_000413 equ $ ; IN [PP2-POWER.BAS] CLEAR NOTES clrf notesH,0 clrf notes,0 F1_000414 equ $ ; IN [PP2-POWER.BAS] SET TIMVALS lfsr 0,TimVals movlw 8 setf POSTINC0,0 decfsz WREG,F,0 bra $ - 4 F1_000415 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__90 bra _LBL__91 _LBL__76 F1_000416 equ $ ; IN [PP2-POWER.BAS] ELSE F1_000418 equ $ ; IN [PP2-POWER.BAS] IF MAXTIM = 1 THEN CLEAR TIME btfss timeHHH,7,0 bra _LBL__93 clrf timeHHH,0 clrf timeHH,0 clrf timeH,0 clrf time,0 _LBL__93 F1_000419 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__91 F1_000420 equ $ ; IN [PP2-POWER.BAS] BTG PORTC.3 btg PORTC,3 F1_000422 equ $ ; IN [PP2-POWER.BAS] GOTO LOOP bra LOOP SortTimers F1_000428 equ $ ; IN [PP2-POWER.BAS] SET IDX setf idx,0 F1_000429 equ $ ; IN [PP2-POWER.BAS] SET NXT.31 bsf NxtHHH,7,0 F1_000430 equ $ ; IN [PP2-POWER.BAS] FOR I = 0 TO 1 clrf _I,0 _FRLB__94 movlw 2 subwf _I,W,0 bc _NXLB__95 F1_000431 equ $ ; IN [PP2-POWER.BAS] IF TIMVALS[I] < NXT THEN bcf STATUS,0,0 rlcf _I,W,0 movwf FSR0L,0 clrf FSR0H,0 rlcf FSR0H,F,0 rlcf FSR0L,F,0 rlcf FSR0H,F,0 movlw 61 addwf FSR0L,F,0 movlw 0 addwfc FSR0H,F,0 movff INDF0,PBP#VAR0 movff PREINC0,PBP#VAR0H movff PREINC0,PBP#VAR0HH movff PREINC0,PBP#VAR0HHH movf Nxt,W,0 subwf PBP#VAR0,W,0 movf NxtH,W,0 subwfb PBP#VAR0H,W,0 movf NxtHH,W,0 subwfb PBP#VAR0HH,W,0 movf NxtHHH,W,0 subwfb PBP#VAR0HHH,W,0 bc _LBL__98 F1_000432 equ $ ; IN [PP2-POWER.BAS] NXT = TIMVALS[I] bcf STATUS,0,0 rlcf _I,W,0 movwf FSR0L,0 clrf FSR0H,0 rlcf FSR0H,F,0 rlcf FSR0L,F,0 rlcf FSR0H,F,0 movlw 61 addwf FSR0L,F,0 movlw 0 addwfc FSR0H,F,0 movff INDF0,Nxt movff PREINC0,NxtH movff PREINC0,NxtHH movff PREINC0,NxtHHH F1_000433 equ $ ; IN [PP2-POWER.BAS] IDX = I movff _I,idx F1_000434 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__98 _CTLB__96 F1_000435 equ $ ; IN [PP2-POWER.BAS] NEXT I incf _I,F,0 bnc _FRLB__94 _NXLB__95 F1_000436 equ $ ; IN [PP2-POWER.BAS] RETURN return 0 KeyPres F1_000441 equ $ ; IN [PP2-POWER.BAS] SELECT NOTEPRES F1_000442 equ $ ; IN [PP2-POWER.BAS] CASE LITE0 movlw 122 subwf notePres,W,0 bnz _LBL__100 F1_000443 equ $ ; IN [PP2-POWER.BAS] PRES0 = PRES movff pres,Pres0 F1_000444 equ $ ; IN [PP2-POWER.BAS] IF PRES0 > 0 THEN movf Pres0,F,0 bz _LBL__103 F1_000445 equ $ ; IN [PP2-POWER.BAS] RATE0 = DUR[PRES0] lfsr 0,Dur bcf STATUS,0,0 rlcf Pres0,W,0 addwf FSR0L,F,0 movlw 0 addwfc FSR0H,F,0 movff POSTINC0,Rate0 movff INDF0,Rate0H bra _LBL__104 _LBL__103 F1_000448 equ $ ; IN [PP2-POWER.BAS] ELSE F1_000449 equ $ ; IN [PP2-POWER.BAS] CLEAR RATE0 clrf Rate0H,0 clrf Rate0,0 F1_000450 equ $ ; IN [PP2-POWER.BAS] CLEAR NOTES.0 bcf notes,0,0 F1_000452 equ $ ; IN [PP2-POWER.BAS] CLEAR VELFLAGS.0 bcf Velflags,0,0 F1_000453 equ $ ; IN [PP2-POWER.BAS] SET TIMVALS[0] setf TimVals#0HHH,0 setf TimVals#0HH,0 setf TimVals#0H,0 setf TimVals#0,0 F1_000454 equ $ ; IN [PP2-POWER.BAS] CLEAR PORTA.3 bcf LATA,3,0 F1_000455 equ $ ; IN [PP2-POWER.BAS] GOSUB SORTTIMERS rcall SortTimers F1_000456 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__104 F1_000457 equ $ ; IN [PP2-POWER.BAS] ENDSELECT _LBL__100 _LBL__99 F1_000461 equ $ ; IN [PP2-POWER.BAS] SET NOTEPRES setf notePres,0 F1_000462 equ $ ; IN [PP2-POWER.BAS] RETURN return 0 ProgChange F1_000465 equ $ ; IN [PP2-POWER.BAS] SET PROG setf prog,0 F1_000466 equ $ ; IN [PP2-POWER.BAS] RETURN return 0 Controller F1_000493 equ $ ; IN [PP2-POWER.BAS] SELECT CTRL F1_000494 equ $ ; IN [PP2-POWER.BAS] CASE 66 movlw 66 subwf Ctrl,W,0 bnz _LBL__106 F1_000496 equ $ ; IN [PP2-POWER.BAS] IF VALUE = 0 THEN movf value,F,0 bnz _LBL__109 F1_000497 equ $ ; IN [PP2-POWER.BAS] GOSUB POWERDOWN rcall PowerDown bra _LBL__110 _LBL__109 F1_000498 equ $ ; IN [PP2-POWER.BAS] ELSE F1_000499 equ $ ; IN [PP2-POWER.BAS] HPWM 2, U_HOLD, FPWM movlw 184 movwf GEN,0 movlw 127 movwf PP1H,0 setf PP1,0 movlw 2 call __HPWM_ F1_000500 equ $ ; IN [PP2-POWER.BAS] HPWM 1, U_VELO, FPWM setf GEN,0 movlw 127 movwf PP1H,0 setf PP1,0 movlw 1 call __HPWM_ F1_000501 equ $ ; IN [PP2-POWER.BAS] HIGH PORTB.2 bcf TRISB,2,0 bsf LATB,2,0 F1_000502 equ $ ; IN [PP2-POWER.BAS] HIGH PORTA.5 bcf TRISA,5,0 bsf LATA,5,0 F1_000503 equ $ ; IN [PP2-POWER.BAS] HIGH PORTA.4 bcf TRISA,4,0 bsf LATA,4,0 F1_000504 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__110 bra _LBL__105 _LBL__106 F1_000505 equ $ ; IN [PP2-POWER.BAS] CASE 90 movlw 90 subwf Ctrl,W,0 bnz _LBL__112 F1_000507 equ $ ; IN [PP2-POWER.BAS] VALUE = VALUE << 1 bcf STATUS,0,0 rlcf value,F,0 F1_000508 equ $ ; IN [PP2-POWER.BAS] HPWM 2, VALUE, FPWM movff value,GEN movlw 127 movwf PP1H,0 setf PP1,0 movlw 2 call __HPWM_ F1_000509 equ $ ; IN [PP2-POWER.BAS] IF VALUE <> U_HOLD THEN movlw 184 subwf value,W,0 bz _LBL__114 F1_000510 equ $ ; IN [PP2-POWER.BAS] HIGH PORTC.5 bcf TRISC,5,0 bsf LATC,5,0 bra _LBL__115 _LBL__114 F1_000511 equ $ ; IN [PP2-POWER.BAS] ELSE F1_000512 equ $ ; IN [PP2-POWER.BAS] LOW PORTC.5 bcf TRISC,5,0 bcf LATC,5,0 F1_000513 equ $ ; IN [PP2-POWER.BAS] ENDIF _LBL__115 bra _LBL__105 _LBL__112 F1_000514 equ $ ; IN [PP2-POWER.BAS] CASE 91 movlw 91 subwf Ctrl,W,0 bnz _LBL__117 F1_000516 equ $ ; IN [PP2-POWER.BAS] VALUE = VALUE << 1 bcf STATUS,0,0 rlcf value,F,0 F1_000517 equ $ ; IN [PP2-POWER.BAS] HPWM 1, VALUE, FPWM movff value,GEN movlw 127 movwf PP1H,0 setf PP1,0 movlw 1 call __HPWM_ bra _LBL__105 _LBL__117 F1_000518 equ $ ; IN [PP2-POWER.BAS] CASE 123 movlw 123 subwf Ctrl,W,0 bnz _LBL__119 F1_000519 equ $ ; IN [PP2-POWER.BAS] CLEAR PORTA.3 bcf LATA,3,0 F1_000520 equ $ ; IN [PP2-POWER.BAS] CLEAR VELFLAGS clrf VelflagsH,0 clrf Velflags,0 F1_000521 equ $ ; IN [PP2-POWER.BAS] CLEAR NOTES clrf notesH,0 clrf notes,0 F1_000522 equ $ ; IN [PP2-POWER.BAS] SET TIMVALS lfsr 0,TimVals movlw 8 setf POSTINC0,0 decfsz WREG,F,0 bra $ - 4 F1_000523 equ $ ; IN [PP2-POWER.BAS] GOSUB SORTTIMERS rcall SortTimers F1_000524 equ $ ; IN [PP2-POWER.BAS] END SELECT _LBL__119 _LBL__105 F1_000525 equ $ ; IN [PP2-POWER.BAS] SET CTRL setf Ctrl,0 F1_000526 equ $ ; IN [PP2-POWER.BAS] RETURN return 0 PowerDown F1_000531 equ $ ; IN [PP2-POWER.BAS] LOW PORTA.4 bcf TRISA,4,0 bcf LATA,4,0 F1_000532 equ $ ; IN [PP2-POWER.BAS] LOW PORTB.2 bcf TRISB,2,0 bcf LATB,2,0 F1_000533 equ $ ; IN [PP2-POWER.BAS] LOW PORTA.5 bcf TRISA,5,0 bcf LATA,5,0 F1_000535 equ $ ; IN [PP2-POWER.BAS] HPWM 2, 0, FPWM clrf GEN,0 movlw 127 movwf PP1H,0 setf PP1,0 movlw 2 call __HPWM_ F1_000536 equ $ ; IN [PP2-POWER.BAS] LOW PORTC.5 bcf TRISC,5,0 bcf LATC,5,0 F1_000537 equ $ ; IN [PP2-POWER.BAS] HPWM 1, 0, FPWM clrf GEN,0 movlw 127 movwf PP1H,0 setf PP1,0 movlw 1 call __HPWM_ F1_000538 equ $ ; IN [PP2-POWER.BAS] LOW PORTA.3 bcf TRISA,3,0 bcf LATA,3,0 F1_000539 equ $ ; IN [PP2-POWER.BAS] CLEAR VELFLAGS clrf VelflagsH,0 clrf Velflags,0 F1_000540 equ $ ; IN [PP2-POWER.BAS] CLEAR NOTES clrf notesH,0 clrf notes,0 F1_000541 equ $ ; IN [PP2-POWER.BAS] SET TIMVALS lfsr 0,TimVals movlw 8 setf POSTINC0,0 decfsz WREG,F,0 bra $ - 4 F1_000543 equ $ ; IN [PP2-POWER.BAS] CLEAR RATE0 clrf Rate0H,0 clrf Rate0,0 F1_000544 equ $ ; IN [PP2-POWER.BAS] CLEAR PRES0 clrf Pres0,0 F1_000545 equ $ ; IN [PP2-POWER.BAS] GOSUB SORTTIMERS bra SortTimers Dur_Lookup F1_000550 equ $ ; IN [PP2-POWER.BAS] SET DUR[0] movlb 1 setf Dur#0H,1 setf Dur#0,1 F1_000554 equ $ ; IN [PP2-POWER.BAS] DUR[1] = 23674 movlw 92 movwf Dur#1H,1 movlw 122 movwf Dur#1,1 F1_000555 equ $ ; IN [PP2-POWER.BAS] DUR[2] = 22917 movlw 89 movwf Dur#2H,1 movlw 133 movwf Dur#2,1 F1_000556 equ $ ; IN [PP2-POWER.BAS] DUR[3] = 22548 movlw 88 movwf Dur#3H,1 movlw 20 movwf Dur#3,1 F1_000557 equ $ ; IN [PP2-POWER.BAS] DUR[4] = 22185 movlw 86 movwf Dur#4H,1 movlw 169 movwf Dur#4,1 F1_000558 equ $ ; IN [PP2-POWER.BAS] DUR[5] = 21827 movlw 85 movwf Dur#5H,1 movlw 67 movwf Dur#5,1 F1_000559 equ $ ; IN [PP2-POWER.BAS] DUR[6] = 21475 movlw 83 movwf Dur#6H,1 movlw 227 movwf Dur#6,1 F1_000560 equ $ ; IN [PP2-POWER.BAS] DUR[7] = 21129 movlw 82 movwf Dur#7H,1 movlw 137 movwf Dur#7,1 F1_000561 equ $ ; IN [PP2-POWER.BAS] DUR[8] = 20789 movlw 81 movwf Dur#8H,1 movlw 53 movwf Dur#8,1 F1_000562 equ $ ; IN [PP2-POWER.BAS] DUR[9] = 20454 movlw 79 movwf Dur#9H,1 movlw 230 movwf Dur#9,1 F1_000563 equ $ ; IN [PP2-POWER.BAS] DUR[10] = 20124 movlw 78 movwf Dur#10H,1 movlw 156 movwf Dur#10,1 F1_000564 equ $ ; IN [PP2-POWER.BAS] DUR[11] = 19800 movlw 77 movwf Dur#11H,1 movlw 88 movwf Dur#11,1 F1_000565 equ $ ; IN [PP2-POWER.BAS] DUR[12] = 19481 movlw 76 movwf Dur#12H,1 movlw 25 movwf Dur#12,1 F1_000566 equ $ ; IN [PP2-POWER.BAS] DUR[13] = 19167 movlw 74 movwf Dur#13H,1 movlw 223 movwf Dur#13,1 F1_000567 equ $ ; IN [PP2-POWER.BAS] DUR[14] = 18858 movlw 73 movwf Dur#14H,1 movlw 170 movwf Dur#14,1 F1_000568 equ $ ; IN [PP2-POWER.BAS] DUR[15] = 18554 movlw 72 movwf Dur#15H,1 movlw 122 movwf Dur#15,1 F1_000569 equ $ ; IN [PP2-POWER.BAS] DUR[16] = 18255 movlw 71 movwf Dur#16H,1 movlw 79 movwf Dur#16,1 F1_000570 equ $ ; IN [PP2-POWER.BAS] DUR[17] = 17961 movlw 70 movwf Dur#17H,1 movlw 41 movwf Dur#17,1 F1_000571 equ $ ; IN [PP2-POWER.BAS] DUR[18] = 17672 movlw 69 movwf Dur#18H,1 movlw 8 movwf Dur#18,1 F1_000572 equ $ ; IN [PP2-POWER.BAS] DUR[19] = 17387 movlw 67 movwf Dur#19H,1 movlw 235 movwf Dur#19,1 F1_000573 equ $ ; IN [PP2-POWER.BAS] DUR[20] = 17107 movlw 66 movwf Dur#20H,1 movlw 211 movwf Dur#20,1 F1_000574 equ $ ; IN [PP2-POWER.BAS] DUR[21] = 16831 movlw 65 movwf Dur#21H,1 movlw 191 movwf Dur#21,1 F1_000575 equ $ ; IN [PP2-POWER.BAS] DUR[22] = 16560 movlw 64 movwf Dur#22H,1 movlw 176 movwf Dur#22,1 F1_000576 equ $ ; IN [PP2-POWER.BAS] DUR[23] = 16293 movlw 63 movwf Dur#23H,1 movlw 165 movwf Dur#23,1 F1_000577 equ $ ; IN [PP2-POWER.BAS] DUR[24] = 16030 movlw 62 movwf Dur#24H,1 movlw 158 movwf Dur#24,1 F1_000578 equ $ ; IN [PP2-POWER.BAS] DUR[25] = 15772 movlw 61 movwf Dur#25H,1 movlw 156 movwf Dur#25,1 F1_000579 equ $ ; IN [PP2-POWER.BAS] DUR[26] = 15518 movlw 60 movwf Dur#26H,1 movlw 158 movwf Dur#26,1 F1_000580 equ $ ; IN [PP2-POWER.BAS] DUR[27] = 15268 movlw 59 movwf Dur#27H,1 movlw 164 movwf Dur#27,1 F1_000581 equ $ ; IN [PP2-POWER.BAS] DUR[28] = 15022 movlw 58 movwf Dur#28H,1 movlw 174 movwf Dur#28,1 F1_000582 equ $ ; IN [PP2-POWER.BAS] DUR[29] = 14780 movlw 57 movwf Dur#29H,1 movlw 188 movwf Dur#29,1 F1_000583 equ $ ; IN [PP2-POWER.BAS] DUR[30] = 14542 movlw 56 movwf Dur#30H,1 movlw 206 movwf Dur#30,1 F1_000584 equ $ ; IN [PP2-POWER.BAS] DUR[31] = 14307 movlw 55 movwf Dur#31H,1 movlw 227 movwf Dur#31,1 F1_000585 equ $ ; IN [PP2-POWER.BAS] DUR[32] = 14077 movlw 54 movwf Dur#32H,1 movlw 253 movwf Dur#32,1 F1_000586 equ $ ; IN [PP2-POWER.BAS] DUR[33] = 13850 movlw 54 movwf Dur#33H,1 movlw 26 movwf Dur#33,1 F1_000587 equ $ ; IN [PP2-POWER.BAS] DUR[34] = 13627 movlw 53 movwf Dur#34H,1 movlw 59 movwf Dur#34,1 F1_000588 equ $ ; IN [PP2-POWER.BAS] DUR[35] = 13407 movlw 52 movwf Dur#35H,1 movlw 95 movwf Dur#35,1 F1_000589 equ $ ; IN [PP2-POWER.BAS] DUR[36] = 13191 movlw 51 movwf Dur#36H,1 movlw 135 movwf Dur#36,1 F1_000590 equ $ ; IN [PP2-POWER.BAS] DUR[37] = 12978 movlw 50 movwf Dur#37H,1 movlw 178 movwf Dur#37,1 F1_000591 equ $ ; IN [PP2-POWER.BAS] DUR[38] = 12769 movlw 49 movwf Dur#38H,1 movlw 225 movwf Dur#38,1 F1_000592 equ $ ; IN [PP2-POWER.BAS] DUR[39] = 12564 movlw 49 movwf Dur#39H,1 movlw 20 movwf Dur#39,1 F1_000593 equ $ ; IN [PP2-POWER.BAS] DUR[40] = 12361 movlw 48 movwf Dur#40H,1 movlw 73 movwf Dur#40,1 F1_000594 equ $ ; IN [PP2-POWER.BAS] DUR[41] = 12162 movlw 47 movwf Dur#41H,1 movlw 130 movwf Dur#41,1 F1_000595 equ $ ; IN [PP2-POWER.BAS] DUR[42] = 11966 movlw 46 movwf Dur#42H,1 movlw 190 movwf Dur#42,1 F1_000596 equ $ ; IN [PP2-POWER.BAS] DUR[43] = 11773 movlw 45 movwf Dur#43H,1 movlw 253 movwf Dur#43,1 F1_000597 equ $ ; IN [PP2-POWER.BAS] DUR[44] = 11583 movlw 45 movwf Dur#44H,1 movlw 63 movwf Dur#44,1 F1_000598 equ $ ; IN [PP2-POWER.BAS] DUR[45] = 11397 movlw 44 movwf Dur#45H,1 movlw 133 movwf Dur#45,1 F1_000599 equ $ ; IN [PP2-POWER.BAS] DUR[46] = 11213 movlw 43 movwf Dur#46H,1 movlw 205 movwf Dur#46,1 F1_000600 equ $ ; IN [PP2-POWER.BAS] DUR[47] = 11032 movlw 43 movwf Dur#47H,1 movlw 24 movwf Dur#47,1 F1_000601 equ $ ; IN [PP2-POWER.BAS] DUR[48] = 10855 movlw 42 movwf Dur#48H,1 movlw 103 movwf Dur#48,1 F1_000602 equ $ ; IN [PP2-POWER.BAS] DUR[49] = 10680 movlw 41 movwf Dur#49H,1 movlw 184 movwf Dur#49,1 F1_000603 equ $ ; IN [PP2-POWER.BAS] DUR[50] = 10508 movlw 41 movwf Dur#50H,1 movlw 12 movwf Dur#50,1 F1_000604 equ $ ; IN [PP2-POWER.BAS] DUR[51] = 10338 movlw 40 movwf Dur#51H,1 movlw 98 movwf Dur#51,1 F1_000605 equ $ ; IN [PP2-POWER.BAS] DUR[52] = 10172 movlw 39 movwf Dur#52H,1 movlw 188 movwf Dur#52,1 F1_000606 equ $ ; IN [PP2-POWER.BAS] DUR[53] = 10008 movlw 39 movwf Dur#53H,1 movlw 24 movwf Dur#53,1 F1_000607 equ $ ; IN [PP2-POWER.BAS] DUR[54] = 9846 movlw 38 movwf Dur#54H,1 movlw 118 movwf Dur#54,1 F1_000608 equ $ ; IN [PP2-POWER.BAS] DUR[55] = 9688 movlw 37 movwf Dur#55H,1 movlw 216 movwf Dur#55,1 F1_000609 equ $ ; IN [PP2-POWER.BAS] DUR[56] = 9532 movlw 37 movwf Dur#56H,1 movlw 60 movwf Dur#56,1 F1_000610 equ $ ; IN [PP2-POWER.BAS] DUR[57] = 9378 movlw 36 movwf Dur#57H,1 movlw 162 movwf Dur#57,1 F1_000611 equ $ ; IN [PP2-POWER.BAS] DUR[58] = 9227 movlw 36 movwf Dur#58H,1 movlw 11 movwf Dur#58,1 F1_000612 equ $ ; IN [PP2-POWER.BAS] DUR[59] = 9078 movlw 35 movwf Dur#59H,1 movlw 118 movwf Dur#59,1 F1_000613 equ $ ; IN [PP2-POWER.BAS] DUR[60] = 8932 movlw 34 movwf Dur#60H,1 movlw 228 movwf Dur#60,1 F1_000614 equ $ ; IN [PP2-POWER.BAS] DUR[61] = 8788 movlw 34 movwf Dur#61H,1 movlw 84 movwf Dur#61,1 F1_000615 equ $ ; IN [PP2-POWER.BAS] DUR[62] = 8646 movlw 33 movwf Dur#62H,1 movlw 198 movwf Dur#62,1 F1_000616 equ $ ; IN [PP2-POWER.BAS] DUR[63] = 8507 movlw 33 movwf Dur#63H,1 movlw 59 movwf Dur#63,1 F1_000617 equ $ ; IN [PP2-POWER.BAS] DUR[64] = 8370 movlw 32 movwf Dur#64H,1 movlw 178 movwf Dur#64,1 F1_000618 equ $ ; IN [PP2-POWER.BAS] DUR[65] = 8235 movlw 32 movwf Dur#65H,1 movlw 43 movwf Dur#65,1 F1_000619 equ $ ; IN [PP2-POWER.BAS] DUR[66] = 8102 movlw 31 movwf Dur#66H,1 movlw 166 movwf Dur#66,1 F1_000620 equ $ ; IN [PP2-POWER.BAS] DUR[67] = 7972 movlw 31 movwf Dur#67H,1 movlw 36 movwf Dur#67,1 F1_000621 equ $ ; IN [PP2-POWER.BAS] DUR[68] = 7843 movlw 30 movwf Dur#68H,1 movlw 163 movwf Dur#68,1 F1_000622 equ $ ; IN [PP2-POWER.BAS] DUR[69] = 7717 movlw 30 movwf Dur#69H,1 movlw 37 movwf Dur#69,1 F1_000623 equ $ ; IN [PP2-POWER.BAS] DUR[70] = 7593 movlw 29 movwf Dur#70H,1 movlw 169 movwf Dur#70,1 F1_000624 equ $ ; IN [PP2-POWER.BAS] DUR[71] = 7470 movlw 29 movwf Dur#71H,1 movlw 46 movwf Dur#71,1 F1_000625 equ $ ; IN [PP2-POWER.BAS] DUR[72] = 7350 movlw 28 movwf Dur#72H,1 movlw 182 movwf Dur#72,1 F1_000626 equ $ ; IN [PP2-POWER.BAS] DUR[73] = 7231 movlw 28 movwf Dur#73H,1 movlw 63 movwf Dur#73,1 F1_000627 equ $ ; IN [PP2-POWER.BAS] DUR[74] = 7115 movlw 27 movwf Dur#74H,1 movlw 203 movwf Dur#74,1 F1_000628 equ $ ; IN [PP2-POWER.BAS] DUR[75] = 7000 movlw 27 movwf Dur#75H,1 movlw 88 movwf Dur#75,1 F1_000629 equ $ ; IN [PP2-POWER.BAS] DUR[76] = 6888 movlw 26 movwf Dur#76H,1 movlw 232 movwf Dur#76,1 F1_000630 equ $ ; IN [PP2-POWER.BAS] DUR[77] = 6777 movlw 26 movwf Dur#77H,1 movlw 121 movwf Dur#77,1 F1_000631 equ $ ; IN [PP2-POWER.BAS] DUR[78] = 6667 movlw 26 movwf Dur#78H,1 movlw 11 movwf Dur#78,1 F1_000632 equ $ ; IN [PP2-POWER.BAS] DUR[79] = 6560 movlw 25 movwf Dur#79H,1 movlw 160 movwf Dur#79,1 F1_000633 equ $ ; IN [PP2-POWER.BAS] DUR[80] = 6454 movlw 25 movwf Dur#80H,1 movlw 54 movwf Dur#80,1 F1_000634 equ $ ; IN [PP2-POWER.BAS] DUR[81] = 6350 movlw 24 movwf Dur#81H,1 movlw 206 movwf Dur#81,1 F1_000635 equ $ ; IN [PP2-POWER.BAS] DUR[82] = 6248 movlw 24 movwf Dur#82H,1 movlw 104 movwf Dur#82,1 F1_000636 equ $ ; IN [PP2-POWER.BAS] DUR[83] = 6147 movlw 24 movwf Dur#83H,1 movlw 3 movwf Dur#83,1 F1_000637 equ $ ; IN [PP2-POWER.BAS] DUR[84] = 6048 movlw 23 movwf Dur#84H,1 movlw 160 movwf Dur#84,1 F1_000638 equ $ ; IN [PP2-POWER.BAS] DUR[85] = 5951 movlw 23 movwf Dur#85H,1 movlw 63 movwf Dur#85,1 F1_000639 equ $ ; IN [PP2-POWER.BAS] DUR[86] = 5855 movlw 22 movwf Dur#86H,1 movlw 223 movwf Dur#86,1 F1_000640 equ $ ; IN [PP2-POWER.BAS] DUR[87] = 5760 movlw 22 movwf Dur#87H,1 movlw 128 movwf Dur#87,1 F1_000641 equ $ ; IN [PP2-POWER.BAS] DUR[88] = 5668 movlw 22 movwf Dur#88H,1 movlw 36 movwf Dur#88,1 F1_000642 equ $ ; IN [PP2-POWER.BAS] DUR[89] = 5576 movlw 21 movwf Dur#89H,1 movlw 200 movwf Dur#89,1 F1_000643 equ $ ; IN [PP2-POWER.BAS] DUR[90] = 5486 movlw 21 movwf Dur#90H,1 movlw 110 movwf Dur#90,1 F1_000644 equ $ ; IN [PP2-POWER.BAS] DUR[91] = 5398 movlw 21 movwf Dur#91H,1 movlw 22 movwf Dur#91,1 F1_000645 equ $ ; IN [PP2-POWER.BAS] DUR[92] = 5311 movlw 20 movwf Dur#92H,1 movlw 191 movwf Dur#92,1 F1_000646 equ $ ; IN [PP2-POWER.BAS] DUR[93] = 5225 movlw 20 movlb 2 movwf Dur#93H,1 movlw 105 movlb 1 movwf Dur#93,1 F1_000647 equ $ ; IN [PP2-POWER.BAS] DUR[94] = 5141 movlw 20 movlb 2 movwf Dur#94H,1 movlw 21 movwf Dur#94,1 F1_000648 equ $ ; IN [PP2-POWER.BAS] DUR[95] = 5058 movlw 19 movwf Dur#95H,1 movlw 194 movwf Dur#95,1 F1_000649 equ $ ; IN [PP2-POWER.BAS] DUR[96] = 4977 movlw 19 movwf Dur#96H,1 movlw 113 movwf Dur#96,1 F1_000650 equ $ ; IN [PP2-POWER.BAS] DUR[97] = 4897 movlw 19 movwf Dur#97H,1 movlw 33 movwf Dur#97,1 F1_000651 equ $ ; IN [PP2-POWER.BAS] DUR[98] = 4818 movlw 18 movwf Dur#98H,1 movlw 210 movwf Dur#98,1 F1_000652 equ $ ; IN [PP2-POWER.BAS] DUR[99] = 4740 movlw 18 movwf Dur#99H,1 movlw 132 movwf Dur#99,1 F1_000653 equ $ ; IN [PP2-POWER.BAS] DUR[100] = 4664 movlw 18 movwf Dur#100H,1 movlw 56 movwf Dur#100,1 F1_000654 equ $ ; IN [PP2-POWER.BAS] DUR[101] = 4589 movlw 17 movwf Dur#101H,1 movlw 237 movwf Dur#101,1 F1_000655 equ $ ; IN [PP2-POWER.BAS] DUR[102] = 4515 movlw 17 movwf Dur#102H,1 movlw 163 movwf Dur#102,1 F1_000656 equ $ ; IN [PP2-POWER.BAS] DUR[103] = 4442 movlw 17 movwf Dur#103H,1 movlw 90 movwf Dur#103,1 F1_000657 equ $ ; IN [PP2-POWER.BAS] DUR[104] = 4370 movlw 17 movwf Dur#104H,1 movlw 18 movwf Dur#104,1 F1_000658 equ $ ; IN [PP2-POWER.BAS] DUR[105] = 4300 movlw 16 movwf Dur#105H,1 movlw 204 movwf Dur#105,1 F1_000659 equ $ ; IN [PP2-POWER.BAS] DUR[106] = 4231 movlw 16 movwf Dur#106H,1 movlw 135 movwf Dur#106,1 F1_000660 equ $ ; IN [PP2-POWER.BAS] DUR[107] = 4162 movlw 16 movwf Dur#107H,1 movlw 66 movwf Dur#107,1 F1_000661 equ $ ; IN [PP2-POWER.BAS] DUR[108] = 4095 movlw 15 movwf Dur#108H,1 setf Dur#108,1 F1_000662 equ $ ; IN [PP2-POWER.BAS] DUR[109] = 4029 movwf Dur#109H,1 movlw 189 movwf Dur#109,1 F1_000663 equ $ ; IN [PP2-POWER.BAS] DUR[110] = 3964 movlw 15 movwf Dur#110H,1 movlw 124 movwf Dur#110,1 F1_000664 equ $ ; IN [PP2-POWER.BAS] DUR[111] = 3901 movlw 15 movwf Dur#111H,1 movlw 61 movwf Dur#111,1 F1_000665 equ $ ; IN [PP2-POWER.BAS] DUR[112] = 3838 movlw 14 movwf Dur#112H,1 movlw 254 movwf Dur#112,1 F1_000666 equ $ ; IN [PP2-POWER.BAS] DUR[113] = 3776 movlw 14 movwf Dur#113H,1 movlw 192 movwf Dur#113,1 F1_000667 equ $ ; IN [PP2-POWER.BAS] DUR[114] = 3715 movlw 14 movwf Dur#114H,1 movlw 131 movwf Dur#114,1 F1_000668 equ $ ; IN [PP2-POWER.BAS] DUR[115] = 3655 movlw 14 movwf Dur#115H,1 movlw 71 movwf Dur#115,1 F1_000669 equ $ ; IN [PP2-POWER.BAS] DUR[116] = 3596 movlw 14 movwf Dur#116H,1 movlw 12 movwf Dur#116,1 F1_000670 equ $ ; IN [PP2-POWER.BAS] DUR[117] = 3538 movlw 13 movwf Dur#117H,1 movlw 210 movwf Dur#117,1 F1_000671 equ $ ; IN [PP2-POWER.BAS] DUR[118] = 3481 movlw 13 movwf Dur#118H,1 movlw 153 movwf Dur#118,1 F1_000672 equ $ ; IN [PP2-POWER.BAS] DUR[119] = 3425 movlw 13 movwf Dur#119H,1 movlw 97 movwf Dur#119,1 F1_000673 equ $ ; IN [PP2-POWER.BAS] DUR[120] = 3370 movlw 13 movwf Dur#120H,1 movlw 42 movwf Dur#120,1 F1_000674 equ $ ; IN [PP2-POWER.BAS] DUR[121] = 3316 movlw 12 movwf Dur#121H,1 movlw 244 movwf Dur#121,1 F1_000675 equ $ ; IN [PP2-POWER.BAS] DUR[122] = 3262 movlw 12 movwf Dur#122H,1 movlw 190 movwf Dur#122,1 F1_000676 equ $ ; IN [PP2-POWER.BAS] DUR[123] = 3210 movlw 12 movwf Dur#123H,1 movlw 138 movwf Dur#123,1 F1_000677 equ $ ; IN [PP2-POWER.BAS] DUR[124] = 3158 movlw 12 movwf Dur#124H,1 movlw 86 movwf Dur#124,1 F1_000678 equ $ ; IN [PP2-POWER.BAS] DUR[125] = 3107 movlw 12 movwf Dur#125H,1 movlw 35 movwf Dur#125,1 F1_000679 equ $ ; IN [PP2-POWER.BAS] DUR[126] = 3057 movlw 11 movwf Dur#126H,1 movlw 241 movwf Dur#126,1 F1_000680 equ $ ; IN [PP2-POWER.BAS] DUR[127] = 3008 movlw 11 movwf Dur#127H,1 movlw 192 movwf Dur#127,1 F1_000681 equ $ ; IN [PP2-POWER.BAS] RETURN movlb 0 return 0 F1_EOF equ $ ; PP2-POWER.BAS _PBLB__120 bra _PBLB__120 __EOF config DEBUG = off config XINST = off config STVREN = off config FCMEN = off config OSC = HSPLL config IESO = off config WDT = off config WDTPS = 128 config BOREN = SBORDIS config BORV = 2 config MCLRE = on config LPT1OSC = on config PBADEN = off config CCP2MX = PORTC config LVP = off config CP0 = off config CP1 = off config CPB = off config CPD = off config WRT0 = off config WRT1 = off config WRTB = off config WRTC = off config WRTD = off config EBTR0 = off config EBTR1 = off config EBTRB = off config PWRT = on end